Travelled to:1 × Portugal
3 × USA
Collaborated with:S.Dey C.Zhao C.N.Taylor L.Zhuang J.Zhang B.Ng Y.Tang J.Shi K.Zheng H.Wang H.Lin L.Shao
Talks about:interconnect (1) manufactur (1) constraint (1) technolog (1) platform (1) nanomet (1) circuit (1) robust (1) negoti (1) insert (1)
Person: Yi Zhao
DBLP: Zhao:Yi
Contributed to:
2009
2005
20042001Wrote 4 papers:
- OOPSLA-2009-ZhaoSZWLS #java #manycore #platform
- Allocation wall: a limiting factor of Java applications on emerging multi-core platforms (YZ, JS, KZ, HW, HL, LS), pp. 361–376.
- DAC-2005-ZhaoZD #constraints #robust
- Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits (CZ, YZ, SD), pp. 190–195.
- ICEIS-v2-2004-ZhuangZNTZ #execution #realtime
- Dynamic Negotiation for Real-Time Manufacturing Execution (LZ, JZ, BN, YT, YZ), pp. 321–326.
- DAC-2001-TaylorDZ #energy #modelling
- Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies (CNT, SD, YZ), pp. 754–757.