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Travelled to:
1 × China
1 × France
1 × USA
Collaborated with:
J.Yan Y.Lin C.Chiang
Talks about:
rectilinear (1) electromigr (1) placement (1) constrain (1) approach (1) untangl (1) steiner (1) obstacl (1) multipl (1) detour (1)

Person: Zhi-Wei Chen

DBLP DBLP: Chen:Zhi=Wei

Contributed to:

DATE 20112011
DAC 20102010
ICPR v2 20062006

Wrote 4 papers:

DATE-2011-ChenY #design
Timing-constrained I/O buffer placement for flip-chip designs (ZWC, JTY), pp. 619–624.
DATE-2011-YanC #multi
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance (JTY, ZWC), pp. 449–454.
DAC-2010-YanC
Two-sided single-detour untangling for bus routing (JTY, ZWC), pp. 206–211.
ICPR-v2-2006-ChenLC #approach
In this paper, an approach for deaf-people (ZWC, YCL, CCC), pp. 104–107.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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