3 papers:
DATE-2005-MullerTAL #design #multi #power management #top-down- Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit (PM, AT, SMA, YL), pp. 258–263.
- EDTC-1997-Gonzalez-TorresMH #set
- Full custom chip set for high speed serial communications up to 2.48 Gbit/s (JGT, PAM, JMH), p. 614.
- EDTC-1997-RiescoDMCSJ #multi #network #on the
- On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC (JR, JCD, LAM, JLC, CS, EJM), pp. 218–222.
