9 papers:
DATE-2014-Huang #performance- A high performance SEU-tolerant latch for nanoscale CMOS technology (ZH), pp. 1–5.
- DATE-2014-JunsangsriLH #concurrent #detection #hybrid
- A hybrid non-volatile SRAM cell with concurrent SEU detection and correction (PJ, FL, JH), pp. 1–4.
- DATE-2012-MohammadiEEM #fault #injection #named
- SCFIT: A FPGA-based fault injection technique for SEU fault model (AM, ME, AE, SGM), pp. 586–589.
- DATE-2009-GolshanB #composition #design
- SEU-aware resource binding for modular redundancy based designs on FPGAs (SG, EB), pp. 1124–1129.
DAC-2008-GargNK #design #performance- A fast, analytical estimator for the SEU-induced pulse width in combinational designs (RG, CN, SPK), pp. 918–923.
- DAC-2007-GolshanB
- Single-Event-Upset (SEU) Awareness in FPGA Routing (SG, EB), pp. 330–333.
- DAC-2005-Heidergott #design
- SEU tolerant device, circuit and processor design (WH), pp. 5–10.
- DATE-v1-2004-LeveugleA #fault #injection
- Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow (RL, AA), pp. 590–595.
- DATE-2001-BensoCNP #analysis #distributed #fault #injection #open source
- SEU effect analysis in an open-source router via a distributed fault injection environment (AB, SDC, GDN, PP), pp. 219–225.
