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simul (8)
model (7)
circuit (6)
parallel (4)
time (3)

Stem spice$ (all stems)

20 papers:

DACDAC-2015-ChenSC #flexibility
A SPICE model of flexible transition metal dichalcogenide field-effect transistors (YYC, ZS, DC), p. 6.
DATEDATE-2015-ChenWY #parallel #performance
A fast parallel sparse solver for SPICE-based circuit simulators (XC, YW, HY), pp. 205–210.
DATEDATE-2015-LiJHWCGLKW #design #optimisation #using
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model (HL, ZJ, PH, YW, HYC, BG, XYL, JFK, HSPW), pp. 1425–1430.
DATEDATE-2014-GholipourCSC #modelling #scalability
Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling (MG, YYC, AS, DC), pp. 1–6.
RERE-2014-LiHMGGB0 #non-functional #ontology #requirements
Non-functional requirements as qualities, with a spice of ontology (FLL, JH, JM, RSSG, GG, AB, LL), pp. 293–302.
DACDAC-2013-HanZF #gpu #named #parallel #simulation
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations (LH, XZ, ZF), p. 8.
DATEDATE-2013-ChenRSIFC #analysis #process
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation (YYC, AR, AS, GI, GF, DC), pp. 1789–1794.
DATEDATE-2013-LyrasRPS #multi #scalability #simulation
Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems (GL, DR, AP, DS), pp. 655–658.
DACDAC-2012-ZhaoF #on the fly #performance #simulation #towards
Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners (XZ, ZF), pp. 1119–1124.
PPoPPPPoPP-2011-FengGH #commit #named #parallel #scalability
SpiceC: scalable parallelism via implicit copying and explicit commit (MF, RG, YH), pp. 69–80.
DATEDATE-2009-KirchnerBG #simulation #using
Analogue mixed signal simulation using spice and SystemC (TK, NB, CG), pp. 284–287.
CGOCGO-2008-RamanVRA #execution #named #parallel
Spice: speculative parallel iteration chunk execution (ER, NV, RR, DIA), pp. 175–184.
ICEISICEIS-ISAS-2006-GrimanPM #approach #development #guidelines #process
Methodological Guidelines for SQA in Development Process — An Approach Based on the SPICE Model (AG, MAP, LEM), pp. 269–275.
DATEDATE-DF-2004-Thiel #validation
Have I Really Met Timing? — Validating PrimeTime Timing Reports with Spice (TT), pp. 114–119.
DATEDATE-v2-2004-JiangC #named
SCORE: SPICE COmpatible Reluctance Extraction (RJ, CCPC), pp. 948–953.
DATEDATE-2000-Perez-MontesMDFR #named
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool (FMPM, FM, RDC, FVF, ÁRV), p. 739.
SACSAC-1995-Beams #approach #development
Adding spice to software development: a software development approach designed for rapidly changing environments (JDB), pp. 384–389.
DACDAC-1993-ChouCC #finite #modelling #performance #simulation #using
High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods (TYC, JC, ZJC), pp. 684–690.
DACDAC-1992-RaghavanBR #named #performance #problem #simulation
AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems (VR, JEB, RAR), pp. 87–92.
DACDAC-1986-FreemanKLN #automation #layout #matrix #modelling
Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning (RDF, SMK, CGLH, MLN), pp. 418–424.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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