BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Used together with:
architectur (3)
core (3)
languag (3)
high (2)
virtual (2)

Stem synthesiz$ (all stems)

9 papers:

DACDAC-2011-AuerbachBCRS #hardware #object-oriented
Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented language (JSA, DFB, PC, RMR, SS), pp. 890–894.
DATEDATE-2011-RahimiLKB #clustering #network
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters (AR, IL, MRK, LB), pp. 491–496.
OOPSLAOOPSLA-2010-AuerbachBCR #architecture #named
Lime: a Java-compatible and synthesizable language for heterogeneous architectures (JSA, DFB, PC, RMR), pp. 89–108.
DACDAC-2009-GluskaL #modelling #verification
Shortening the verification cycle with synthesizable abstract models (AG, LL), pp. 454–459.
PEPMPEPM-2008-GillenwaterMSZTGO #hardware #static typing #using
Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability (JG, GM, CS, AYZ, WT, JG, JO), pp. 41–50.
DATEDATE-2006-KlingaufGG #architecture #named #transaction
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC (WK, HG, RG), pp. 1318–1323.
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding (FK, TB, NW), pp. 100–105.
DATEDATE-DF-2004-WortmannSM #architecture #performance
A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core (AW, SS, MM), pp. 46–51.
DACDAC-2002-RichardsonHHZSL #cpu
The iCOREtm 520 MHz synthesizable CPU core (NR, LBH, RH, TZ, NS, JL), pp. 640–645.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.