Ashok K. Murugavel, N. Ranganathan
Petri net modeling of gate and interconnect delays for power estimation
DAC, 2002.
@inproceedings{DAC-2002-MurugavelR, author = "Ashok K. Murugavel and N. Ranganathan", booktitle = "{Proceedings of the 39th Design Automation Conference}", doi = "10.1145/513918.514034", isbn = "1-58113-461-4", pages = "455--460", publisher = "{ACM}", title = "{Petri net modeling of gate and interconnect delays for power estimation}", year = 2002, }