BibSLEIGH — interconnect stem

Used together with:

model (60)
chip (54)
network (38)
base (35)
analysi (33)

Stem interconnect$ (all stems)

305 papers:

DAC-2015-BokhariJSHP #architecture #manycore #named: SuperNet: multimode interconnect architecture for manycore chips (HB, HJ, MS, JH, SP), p. 6.
DAC-2015-ChenTSHK #analysis #modelling #multi #reliability: Interconnect reliability modeling and analysis for multi-branch interconnect trees (HBC, SXDT, VS, XH, TK), p. 6.
DAC-2015-CongGHRY #architecture #network: On-chip interconnection network for accelerator-rich architectures (JC, MG, YH, GR, BY), p. 6.
DAC-2015-JangKGY0 #design: Bandwidth-efficient on-chip interconnect designs for GPGPUs (HJ, JK, PG, KHY, EJK), p. 6.
DAC-2015-LiBTO #communication #energy #performance: Complementary communication path for energy efficient on-chip optical interconnects (HL, SLB, YT, IO), p. 6.
DAC-2015-VasudevanR #algorithm #performance: An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form (VV, MR), p. 6.
DATE-2015-AzarkhishRLB #memory management #performance: High performance AXI-4.0 based interconnect for extensible smart memory cubes (EA, DR, IL, LB), pp. 1317–1322.
DATE-2015-DuongNXWTBYWW #analysis: Coherent crosstalk noise analyses in ring-based optical interconnects (LHKD, MN, JX, ZW, YT, SLB, PY, XW, ZW), pp. 501–506.
DATE-2015-HuangTTC #architecture: Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects (SYH, MTT, KHHT, WTC), pp. 924–927.
DATE-2015-KarageorgosSRRT #multi #variability: Impact of interconnect multiple-patterning variability on SRAMs (IK, MS, PR, JR, ZT, DV, RB, SS, WD), pp. 609–612.
DATE-2015-LaerEMWJ #multi #predict: Coherence based message prediction for optically interconnected chip multiprocessors (AVL, CE, MRM, PMW, TMJ), pp. 613–616.
DATE-2015-LiFBLON #design: Thermal aware design method for VCSEL-based on-chip optical interconnect (HL, AF, SLB, XL, IO, GN), pp. 1120–1125.
DATE-2015-MaHJ #manycore: A packet-switched interconnect for many-core systems with BE and RT service (RM, ZH, AJ), pp. 980–983.
DATE-2015-XieKBWPC #design #energy #hybrid #optimisation: Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect (QX, YK, DB, YW, MP, NC), pp. 1607–1610.
DAC-2014-ZhanXS #fine-grained #named: NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era (JZ, YX, GS), p. 6.
DATE-2014-CilardoFGM #communication #manycore #scheduling #synthesis: Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems (AC, EF, LG, AM), pp. 1–4.
DATE-2014-ErbSSB #fault #performance #smt: Efficient SMT-based ATPG for interconnect open defects (DE, KS, MS, BB), pp. 1–6.
DATE-2014-TaouilMHM #3d: Interconnect test for 3D stacked memory-on-logic (MT, MM, SH, EJM), pp. 1–6.
DATE-2014-TurkyilmazCRBC #3d #integration #using: 3D FPGA using high-density interconnect Monolithic Integration (OT, GC, OR, PB, FC), pp. 1–4.
DATE-2014-VillenaS #analysis #network #performance #variability: Efficient analysis of variability impact on interconnect lines and resistor networks (JFV, LMS), pp. 1–6.
SIGMOD-2014-HanW #mining: Mining latent entity structures from massive unstructured and interconnected data (JH, CW), pp. 1409–1410.
DAC-2013-CongX #fault #programmable: Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance (JC, BX), p. 8.
DAC-2013-MishraS #grid #power management: The impact of electromigration in copper interconnects on power grid integrity (VM, SSS), p. 6.
DATE-2013-FettweisHLF: Wireless interconnect for board and chip level (GF, NuH, LL, EF), pp. 958–963.
DATE-2013-Pham-QuocHWABB #design #hardware #hybrid: Hybrid interconnect design for heterogeneous hardware accelerators (CPQ, JH, SW, ZAA, JB, KB), pp. 843–846.
DATE-2013-Xie #memory management: Future memory and interconnect technologies (YX0), pp. 964–969.
DATE-2013-ZhaiYZ #algorithm #float #random: GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects (KZ, WY, HZ), pp. 1661–1666.
HPCA-2013-KoibuchiFMC #random: Layout-conscious random topologies for HPC off-chip interconnects (MK, IF, HM, HC), pp. 484–495.
HPCA-2013-SamihWKMTS #energy: Energy-efficient interconnect via Router Parking (AS, RW, AK, CM, TYCT, YS), pp. 508–519.
HPDC-2013-CuiBLD #optimisation #performance: Virtual TCP offload: optimizing ethernet overlay performance on advanced interconnects (ZC, PGB, JRL, PAD), pp. 49–60.
SOSP-2013-ChandraKZ #web #web service: Asynchronous intrusion recovery for interconnected web services (RC, TK, NZ), pp. 213–227.
DAC-2012-SuYZ #named #order #performance #reduction: AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits (YS, FY, XZ), pp. 295–300.
DATE-2012-DasSHMC #multi: Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores (AD, MS, NH, GM, ANC), pp. 479–484.
VLDB-2012-SunHYY #analysis #approach #mining #network: Mining Knowledge from Interconnected Data: A Heterogeneous Information Network Analysis Approach (YS, JH, XY, PSY), pp. 2022–2023.
CIKM-2012-DragutOMMBS: Lonomics Atlas: a tool to explore interconnected ionomic, genomic and environmental data (ECD, MO, AM, NM, PB, DES), pp. 2680–2682.
MoDELS-2012-HegedusHRV #emf #modelling: Query-Driven Soft Interconnection of EMF Models (ÁH, ÁH, IR, DV), pp. 134–150.
MoDELS-2012-HegedusHRV #emf #modelling: Query-Driven Soft Interconnection of EMF Models (ÁH, ÁH, IR, DV), pp. 134–150.
DAC-2011-ChaiJ #complexity #equation #linear #matrix: Direct matrix solution of linear complexity for surface integral-equation based impedance extraction of high bandwidth interconnects (WC, DJ), pp. 206–211.
DATE-2011-ChaixAZN #adaptation #concurrent #fault tolerance: A fault-tolerant deadlock-free adaptive routing for on chip interconnects (FC, DA, NEZ, MN), pp. 909–912.
DATE-2011-GobbatoCG #megamodelling #parallel #scalability: A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodels (LG, AC, SGT), pp. 26–31.
DATE-2011-OnizawaMH #communication #monitoring: Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring (NO, AM, TH), pp. 776–781.
DATE-2011-RahimiLKB #clustering #network: A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters (AR, IL, MRK, LB), pp. 491–496.
DATE-2011-WohSDKSBM #power management: Low power interconnects for SIMD computers (MW, SS, RGD, DK, DS, DB, TNM), pp. 600–605.
DATE-2011-YoonLJPKPC #configuration management #embedded #incremental #named: I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics (JWY, JL, JJ, SP, YK, YP, DC), pp. 1346–1351.
HPCA-2011-LiHL0DTW #network: Power shifting in Thrifty Interconnection Network (JL, WH, CL, LZ, WED, RRT, KW), pp. 156–167.
ISMM-2011-MajoG #manycore #memory management: Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead (ZM, TRG), pp. 11–20.
DAC-2010-IhrigMJ #automation #design #manycore #modelling: Automated modeling and emulation of interconnect designs for many-core chip multiprocessors (CJI, RGM, AKJ), pp. 431–436.
DAC-2010-Mathewson #evolution #how: The evolution of SOC interconnect and how NOC fits within it (BM), pp. 312–313.
DAC-2010-WuSDDXDL #3d #integration: Cost-driven 3D integration with interconnect layers (XW, GS, XD, RD, YX, CRD, JL), pp. 150–155.
DAC-2010-ZhangL #manycore #network: A multilayer nanophotonic interconnection network for on-chip many-core communications (XZ, AL), pp. 156–161.
DATE-2010-ChanHBBC #analysis #named #network: PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks (JC, GH, AB, KB, LPC), pp. 691–696.
DATE-2010-El-MoselhyD #order #reduction #statistics #using: Variation-aware interconnect extraction using statistical moment preserving model order reduction (TAEM, LD), pp. 453–458.
DATE-2010-JunYC #library #multi #network #synthesis: Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network (MJ, SY, EYC), pp. 1390–1395.
DATE-2010-MahmoodBMMD #modelling #multi #order #programming: Passive reduced order modeling of multiport interconnects via semidefinite programming (ZM, BNB, TM, AM, LD), pp. 622–625.
DATE-2010-SrivastavaSB #3d #performance: Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate (NS, RS, KB), pp. 459–464.
DATE-2010-UgryumovaS #algorithm #modelling #on the: On passivity of the super node algorithm for EM modeling of interconnect systems (MVU, WHAS), pp. 471–476.
DATE-2010-WeerasekeraGPT #3d #on the: On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits (RW, MG, DP, HT), pp. 1325–1328.
DATE-2010-ZengC #metric #using: Interconnect delay and slew metrics using the beta distribution (JKZ, CPC), pp. 1329–1332.
ASPLOS-2010-KirmanM #power management #using: A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing (NK, JFM), pp. 15–28.
DAC-2009-ChouCWCCWW #3d #manycore: No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips (SHC, CCC, CNW, YCC, TFC, CCW, JSW), pp. 587–592.
DAC-2009-LiuX #design #validation: Interconnection fabric design for tracing signals in post-silicon validation (XL, QX), pp. 352–357.
DAC-2009-Pasricha #3d: Exploring serial vertical interconnects for 3D ICs (SP), pp. 581–586.
DAC-2009-YuHZ: Variational capacitance extraction of on-chip interconnects based on continuous surface model (WY, CH, WZ), pp. 758–763.
DATE-2009-ChenW #3d #modelling #simulation: New simulation methodology of 3D surface roughness loss for interconnects modeling (QC, NW), pp. 1184–1189.
DATE-2009-MadduriVBT #manycore #monitoring: A monitor interconnect and support subsystem for multicore processors (SM, RV, WB, RT), pp. 761–766.
DATE-2009-SioziosPS #3d #architecture: A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs (KS, VFP, DS), pp. 172–177.
DATE-2009-VignonCDMF #3d #architecture #novel: A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context (AV, SC, WD, PM, MF), pp. 929–933.
DATE-2009-WangM #using: An accurate interconnect thermal model using equivalent transmission line circuit (BW, PM), pp. 280–283.
PEPM-2009-SalamaMTGO #consistency #dependent type #using: Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions (CS, GM, WT, JG, JO), pp. 121–130.
KEOD-2009-KrempelsPST #development: Interconnected Tool-assistance for Development of Agent-oriented Software Systems (KHK, AP, JvS, CT), pp. 308–314.
KMIS-2009-Garrot-Lavoue #community #framework #information management #web: Interconnection of Communities of Practice — A Web Platform for Knowledge Management (ÉGL), pp. 13–20.
MoDELS-2009-DawV #modelling #process #state machine #uml: Deterministic UML Models for Interconnected Activities and State Machines (ZD, MV), pp. 556–570.
MoDELS-2009-DawV #modelling #process #state machine #uml: Deterministic UML Models for Interconnected Activities and State Machines (ZD, MV), pp. 556–570.
HPCA-2009-AgarwalPJ: In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects (NA, LSP, NKJ), pp. 67–78.
HPCA-2009-DasEMVD #design #evaluation: Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs (RD, SE, AKM, NV, CRD), pp. 175–186.
HPCA-2009-FidalgoVM #adaptation #multi #named #network: MRR: Enabling fully adaptive multicast routing for CMP interconnection networks (PAF, VP, JÁG), pp. 355–366.
HPCA-2009-GrotHKM: Express Cube Topologies for on-Chip Interconnects (BG, JH, SWK, OM), pp. 163–174.
HPCA-2009-XuDZZZY #3d #design #network: A low-radix and low-diameter 3D interconnection network design (YX, YD, BZ, XZ, YZ, JY), pp. 30–42.
HPDC-2009-HurseyML: Interconnect agnostic checkpoint/restart in open MPI (JH, TM, AL), pp. 49–58.
DAC-2008-BalkanQV #hybrid #network #parallel: An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing (AOB, GQ, UV), pp. 435–440.
DAC-2008-Bautista #challenge: Tera-scale computing and interconnect challenges (JB), pp. 665–667.
DAC-2008-HanSE #3d #equation #modelling: Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects (KJH, MS, EE), pp. 421–424.
DAC-2008-MoselhyD #equation #performance #probability: Stochastic integral equation solver for efficient variation-aware interconnect extraction (TM, LD), pp. 415–420.
DATE-2008-Rimolo-DonadioSGKR #analysis #metric #optimisation: Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects (RRD, CS, XG, YHK, MBR), pp. 252–255.
DATE-2008-SrivastavaSB #multi: High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate (NS, RS, KB), pp. 426–431.
DATE-2008-YonedaF #functional #reuse: Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects (TY, HF), pp. 1366–1369.
DATE-2008-ZengC #analysis #polynomial #random: Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis (JKZ, CPC), pp. 1091–1094.
ICPC-2008-FonsecaCHP #behaviour #how #web: How to Interconnect Operational and Behavioral Views of Web Applications (RFCdF, DCdC, PRH, MJVP), pp. 263–267.
HPCA-2008-ChangCKNRST #multi: CMP network-on-chip overlaid with multi-band RF-interconnect (MFC, JC, AK, MN, GR, ES, SWT), pp. 191–202.
LCTES-2008-RajopadhyeGR #configuration management: A domain specific interconnect for reconfigurable computing (SVR, GG, LR), pp. 79–88.
DAC-2007-BernsteinACEGHIKMPY #3d #challenge #design: Interconnects in the Third Dimension: Design Challenges for 3D ICs (KB, PA, JC, PGE, DG, WH, MI, SJK, JM, RP, AMY), pp. 562–567.
DAC-2007-LimKK #architecture #communication #distributed #synthesis: Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture (KHL, YK, TK), pp. 765–770.
DAC-2007-NaeemiSM #modelling #multi #optimisation #performance: Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects (AN, RS, JDM), pp. 568–573.
DAC-2007-Roychowdhury: Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations (JSR), pp. 574–575.
DAC-2007-Scheffer: CAD Implications of New Interconnect Technologies (LS), pp. 576–581.
DAC-2007-XuZC #architecture #fault #optimisation: SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects (QX, YZ, KC), pp. 676–681.
DATE-2007-ChoudhuryRRM #interactive #memory management: Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory (MRC, KR, SR, KM), pp. 1072–1077.
DATE-2007-EachempatiNGVM #architecture: Assessing carbon nanotube bundle interconnect for future FPGA architectures (SE, AN, AG, NV, YM), pp. 307–312.
DATE-2007-FanMTCH #correlation #order #reduction #statistics: Statistical model order reduction for interconnect circuits considering spatial correlations (JF, NM, SXDT, YC, XH), pp. 1508–1513.
DATE-2007-HuMWD #performance: Optimization-based wideband basis functions for efficient interconnect extraction (XH, TM, JKW, LD), pp. 1200–1205.
DATE-2007-KrauseBHTR #component #simulation: Timing simulation of interconnected AUTOSAR software-components (MK, OB, AH, GT, WR), pp. 474–479.
DATE-2007-LeGB #pervasive #verification: Formal verification of a pervasive interconnect bus system in a high-performance microprocessor (TL, TG, JB), pp. 219–224.
DATE-2007-LinH #interactive #reduction #statistics: Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction (YL, LH), pp. 636–641.
DATE-2007-XuRC #analysis #interactive #pipes and filters #power management: Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining (JX, AR, MHC), pp. 1218–1223.
DATE-2007-ZhuZCXZ #grid #probability #process: A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology (HZ, XZ, WC, JX, DZ), pp. 1514–1519.
ICEIS-AIDSS-2007-PrauseKAOC #development #documentation #tool support: Interconnecting Documentation — Harnessing the Different Powers of Current Documentation Tools in Software Development (CP, JK, SA, RO, ABC), pp. 63–68.
SEKE-2007-ZhouKBSC #framework #requirements #specification: A Framework of Hierarchical Requirements Patterns for Specifying Systems of Interconnected Simulink/Stateflow Modules (CZ, RK, DB, KS, DDC), pp. 179–184.
HPCA-2007-Dally: Interconnect-Centric Computing (WJD), p. 1.
HPCA-2007-KatayamaO #memory management: Optical Interconnect Opportunities for Future Server Memory Systems (YK, AO), pp. 46–50.
DAC-2006-BanerjeeS #future of #question: Are carbon nanotubes the future of VLSI interconnections? (KB, NS), pp. 809–814.
DAC-2006-HuebbersDI #parametricity #performance #process: Computation of accurate interconnect process parameter values for performance corners under process variations (FH, AD, YII), pp. 797–800.
DAC-2006-KlingaufGBPB #modelling #named #transaction: GreenBus: a generic interconnect fabric for transaction level modelling (WK, RG, OB, PP, MB), pp. 905–910.
DATE-2006-AbbaspourFP #analysis #statistics: Non-gaussian statistical interconnect timing analysis (SA, HF, MP), pp. 533–538.
DATE-2006-AngioliniMCBR #layout: Contrasting a NoC and a traditional interconnect fabric with layout awareness (FA, PM, SC, LB, LR), pp. 124–129.
DATE-2006-LeeKKCY #adaptation #using: A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes (SJL, KK, HK, NC, HJY), pp. 79–80.
DATE-2006-Liu: A practical method to estimate interconnect responses to variabilities (FL), pp. 545–546.
DATE-2006-OmanaCRM #detection #fault #low cost #reliability: Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects (MO, JMC, DR, CM), pp. 170–175.
DATE-2006-SutharD #detection #fault #multi #online #performance #testing: Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults (VS, SD), pp. 1165–1170.
DATE-DF-2006-DumitrascuBPBJ #flexibility #framework #performance: Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application (FD, IB, LP, MB, AAJ), pp. 166–171.
DATE-DF-2006-MeijerKB #design #energy: Energy-efficient FPGA interconnect design (MM, RK, MTB), pp. 42–47.
DATE-DF-2006-QuaglioVCTM #flexibility #framework: Interconnection framework for high-throughput, flexible LDPC decoders (FQ, FV, CC, AT, GM), pp. 124–129.
FLOPS-2006-PlasmeijerA #programming #web: iData for the World Wide Web — Programming Interconnected Web Forms (RP, PA), pp. 242–258.
ICPR-v4-2006-ZhangMH #feature model #multi #network: Multiscale Feature Extraction of Finger-Vein Patterns Based on Curvelets and Local Interconnection Structure Neural Network (ZZ, SM, XH), pp. 145–148.
DAC-2005-GayasenVI: Exploring technology alternatives for nano-scale FPGA interconnects (AG, NV, MJI), pp. 921–926.
DAC-2005-KimPTVD #adaptation #latency: A low latency router supporting adaptivity for on-chip interconnects (JK, DP, TT, NV, CRD), pp. 559–564.
DAC-2005-NandraDMDHLSA: Interconnects are moving from MHz→GHz should you be afraid?: or... “my giga hertz, does yours?” (NN, PD, RM, JFD, AH, BL, JS, JA), pp. 289–290.
DAC-2005-ZhouMA #reduction: Structure preserving reduction of frequency-dependent interconnect (QZ, KM, ACA), pp. 939–942.
DATE-2005-GangwarBPK #architecture #clustering #evaluation: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures (AG, MB, PRP, AK), pp. 730–735.
DATE-2005-LiLLPN #modelling #order #parametricity #performance #reduction #using #variability: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction (PL, FL, XL, LTP, SRN), pp. 958–963.
DATE-2005-SoensPWD #analysis #simulation: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.
DATE-2005-TsaiVXI #network: Leakage-Aware Interconnect for On-Chip Network (YFT, NV, YX, MJI), pp. 230–231.
DATE-2005-WeberCSW #network: A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips (WDW, JC, IS, DW), pp. 1232–1237.
ICEIS-v4-2005-ShankarSKGO #ad hoc #grid: Dynamic Coalition in Agent Aware Adhoc Virtual P2P Interconnect Grid Computing System — A3PVIGRID (AS, CS, AK, AKG, PO), pp. 170–175.
CIKM-2005-CohenKKS #keyword #semantics #xml: Interconnection semantics for keyword search in XML (SC, YK, BK, YS), pp. 389–396.
SAC-2005-FarahabadyS #multi #network #recursion: The recursive transpose-connected cycles (RTCC) interconnection network for multiprocessors (MHF, HSA), pp. 734–738.
SAC-2005-MonemizadehS #multi #network #scalability: The necklace-hypercube: a well scalable hypercube-based interconnection network for multiprocessors (MM, HSA), pp. 729–733.
HPCA-2005-DuatoJFNGF #effectiveness #multi #network #scalability: A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks (JD, IJ, JF, FN, PJG, TNF), pp. 108–119.
DAC-2004-AgarwalSBLNV #analysis #metric: Variational delay metrics for interconnect timing analysis (KA, DS, DB, FL, SRN, SBKV), pp. 381–384.
DAC-2004-CongFZ #architecture #automation #pipes and filters #synthesis: Architecture-level synthesis for automatic interconnect pipelining (JC, YF, ZZ), pp. 602–607.
DAC-2004-LongSLH #optimisation #pipes and filters: Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects (CL, LJS, WL, LH), pp. 640–645.
DAC-2004-MohiyuddinPAW: Synthesizing interconnect-efficient low density parity check codes (MM, AP, AA, WW), pp. 488–491.
DAC-2004-PlasBVDWDGM #simulation: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
DAC-2004-TanjiA #analysis #distributed: Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects (YT, HA), pp. 810–813.
DAC-2004-WangHL #linear #nondeterminism #parametricity: A linear fractional transform (LFT) based model for interconnect parametric uncertainty (JMW, OH, JL), pp. 375–380.
DAC-2004-ZhangHC #analysis #pipes and filters #statistics: Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining (LZ, YH, CCPC), pp. 904–907.
DATE-v1-2004-CatthoorCMGLMSW #design #how #problem #question #scalability: How Can System-Level Design Solve the Interconnect Technology Scaling Problem? (FC, AC, GM, PG, RL, KM, PvdS, RW), pp. 332–339.
DATE-v1-2004-Fit-FloreaHK #reliability: Enhancing Reliability of Operational Interconnections in FPGAs (AFF, MH, FK), pp. 746–747.
DATE-v1-2004-LiVKI: A Crosstalk Aware Interconnect with Variable Cycle Transmission (LL, NV, MTK, MJI), pp. 102–107.
DATE-v2-2004-ChandraXSP #design #performance: An Interconnect Channel Design Methodology for High Performance Integrated Circuits (VC, AX, HS, LTP), pp. 1138–1143.
DATE-v2-2004-JiangC04a #reduction: Realizable Reduction for Electromagnetically Coupled RLMC Interconnects (RJ, CCPC), pp. 1400–1401.
DATE-v2-2004-NakashimaIOM: ULSI Interconnect Length Distribution Model Considering Core Utilization (HN, JI, KO, KM), pp. 1210–1217.
ICEIS-v4-2004-GaaloulBBG #component #distributed: A Pattern for Interconnecting Distributed Components (WG, KB, KB, CG), pp. 430–434.
DAC-2003-AgarwalSB #effectiveness: An effective capacitance based driver output model for on-chip RLC interconnects (KA, DS, DB), pp. 376–381.
DAC-2003-CroixW #analysis #modelling #using: Blade and razor: cell and interconnect delay analysis using current-based models (JFC, DFW), pp. 386–389.
DAC-2003-GorenZGWBALSTGPJSSDH #design #modelling: On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices (DG, MZ, RG, IAW, AB, AA, BL, AS, YT, RAG, JP, DLJ, SES, RS, CED, DLH), pp. 724–727.
DAC-2003-Kumar #design: Interconnect and noise immunity design for the Pentium 4 processor (RK0), pp. 938–943.
DAC-2003-Tahoori #satisfiability #testing #using: Using satisfiability in application-dependent testing of FPGA interconnects (MBT), pp. 678–681.
DATE-2003-DasguptaKM #architecture #metric #novel #performance: A Novel Metric for Interconnect Architecture Performance (PD, ABK, SM), pp. 10448–10455.
DATE-2003-GerlingSSMT #multi #simulation: Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects (JG, OS, JS, GM, JT), pp. 11110–11111.
DATE-2003-Grivet-TalociaSMC #megamodelling #simulation: Combined FDTD/Macromodel Simulation of Interconnected Digital Devices (SGT, ISS, IAM, FGC), pp. 10536–10541.
DATE-2003-LuK: Interconnect Planning with Local Area Constrained Retiming (RL, CKK), pp. 10442–10447.
DATE-2003-MartorellMA #evaluation #modelling: Modeling and Evaluation of Substrate Noise Induced by Interconnects (FM, DM, XA), pp. 10524–10529.
DATE-2003-PetrotG #api #implementation #lightweight #multi #thread: Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect (FP, PG), pp. 20051–20056.
DATE-2003-YeBM #analysis #communication: Packetized On-Chip Interconnect Communication Analysis for MPSoC (TTY, LB, GDM), pp. 10344–10349.
HT-2003-DaveKFFSDD: Browsing intricately interconnected paths (PD, UK, RF, LFR, FMSI, SD, ZD), pp. 95–103.
HPCA-2003-HoP #communication #design #performance: A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns (WHH, TMP), pp. 377–388.
HPCA-2003-ShangPJ #network #optimisation #scalability: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks (LS, LSP, NKJ), pp. 91–102.
HPCA-2003-TaylorLAA #architecture #network: Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture (MBT, WL, SPA, AA), pp. 341–353.
DAC-2002-CaoLCC #megamodelling #named #power management: HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery (YC, YML, THC, CCPC), pp. 379–384.
DAC-2002-KapurCS #estimation #novel #optimisation #reduction #using: Power estimation in global interconnects and its reduction using a novel repeater optimization methodology (PK, GC, KS), pp. 461–466.
DAC-2002-MurugavelR #estimation #modelling #petri net: Petri net modeling of gate and interconnect delays for power estimation (AKM, NR), pp. 455–460.
DAC-2002-VenkatesanDM #distributed #physics: A physical model for the transient response of capacitively loaded distributed rlc interconnects (RV, JAD, JDM), pp. 763–766.
DATE-2002-BecerZBPH #analysis #using: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model (MRB, VZ, DB, RP, INH), pp. 456–463.
DATE-2002-FavalliM #fault #problem #self: Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths (MF, CM), pp. 612–617.
DATE-2002-GorenZGGLASW #approach #design: An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach (DG, MZ, TCG, RG, BL, AA, AS, IAW), pp. 804–811.
DATE-2002-LuZKC: Flip-Flop and Repeater Insertion for Early Interconnect Planning (RL, GZ, CKK, KYC), pp. 690–695.
DATE-2002-XuM #matrix: Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects (QX, PM), pp. 820–825.
DATE-2002-YmeriNMRSV #approach #parametricity #performance: Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate (HY, BN, KM, DDR, MS, SV), p. 1113.
DAC-2001-AjamiBPG #analysis #performance: Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs (AHA, KB, MP, LPPPvG), pp. 567–572.
DAC-2001-BanerjeeM #analysis #distributed #novel #optimisation #performance #using: Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects (KB, AM), pp. 798–803.
DAC-2001-BeattieP01a #modelling: Modeling Magnetic Coupling for On-Chip Interconnect (MWB, LTP), pp. 335–340.
DAC-2001-ChenBD #embedded #fault #testing #using: Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores (LC, XB, SD), pp. 317–320.
DAC-2001-DallyT #network: Route Packets, Not Wires: On-Chip Interconnection Networks (WJD, BT), pp. 684–689.
DAC-2001-DanielSW #analysis #performance #using: Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and Off-Chip Interconnect (LD, ALSV, JW), pp. 563–566.
DAC-2001-SgroiSMKMRS #design: Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design (MS, MS, AM, KK, SM, JMR, ALSV), pp. 667–672.
DAC-2001-TaylorDZ #energy #modelling: Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies (CNT, SD, YZ), pp. 754–757.
DAC-2001-UchinoC #energy: An Interconnect Energy Model Considering Coupling Effects (TU, JC), pp. 555–558.
DAC-2001-ZhangRKJ #3d #architecture #integration: Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration (RZ, KR, CKK, DBJ), pp. 846–851.
DATE-2001-CappuccinoC #performance: CMOS sizing rule for high performance long interconnects (GC, GC), p. 817.
DATE-2001-HuangM #configuration management #design #network #using: Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks (ZH, SM), p. 735.
TOOLS-EUROPE-2001-FiadeiroA #contract: Interconnecting Objects via Contracts (JLF, LFA), pp. 182–183.
SAC-2001-JangCJJ #multi #network #performance: Efficient schemes to scale the interconnection network bandwidth in a ring-based multiprocessor system (BSJ, SWC, STJ, CSJ), pp. 510–516.
DAC-2000-BaiDR #self: Self-test methodology for at-speed test of crosstalk in chip interconnects (XB, SD, JR), pp. 619–624.
DAC-2000-GadDNA #distributed #multi #order #reduction: Passive model order reduction of multiport distributed interconnects (EG, AD, MSN, RA), pp. 526–531.
DAC-2000-HarrisT #architecture #clustering #testing: Interconnect testing in cluster-based FPGA architectures (IGH, RT), pp. 49–54.
DAC-2000-KahngMS #analysis #on the: On switch factor based analysis of coupled RC interconnects (ABK, SM, ES), pp. 79–84.
DAC-2000-KashyapK: A realizable driving point model for on-chip interconnect with inductance (CVK, BK), pp. 190–195.
DAC-2000-LevySMW #analysis #performance: A rank-one update method for efficient processing of interconnect parasitics in timing analysis (HL, WS, DM, JW), pp. 75–78.
DAC-2000-LiuNPS: Impact of interconnect variations on the clock skew of a gigahertz microprocessor (YL, SRN, LTP, AJS), pp. 168–171.
DAC-2000-MehrotraSBCVN #modelling #performance: A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance (VM, SLS, DSB, AC, RV, SRN), pp. 172–175.
DAC-2000-YuWK #algorithm #network #order #reduction: Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks (QY, JMW, ESK), pp. 520–525.
DATE-2000-GuerrierG #architecture: A Generic Architecture for On-Chip Packet-Switched Interconnections (PG, AG), pp. 250–256.
DATE-2000-Pillkahn #evaluation: Evaluation of Interconnects with TDR (UP), p. 740.
DAC-1999-AlpertDQ: Buffer Insertion with Accurate Gate and Interconnect Delay Computation (CJA, AD, STQ), pp. 479–484.
DAC-1999-BanerjeeMSH #on the: On Thermal Effects in Deep Sub-Micron VLSI Interconnects (KB, AM, ALSV, CH), pp. 885–891.
DAC-1999-ChenM #using: Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (CPC, NM), pp. 502–506.
DAC-1999-CongHX #performance: Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections (JC, YYH, SX), pp. 373–378.
DAC-1999-CongP #design #estimation: Interconnect Estimation and Dlanning for Deep Submicron Designs (JC, DZP), pp. 507–510.
DAC-1999-Freund #algorithm #modelling #simulation: Passive Reduced-Order Models for Interconnect Simulation and Their Computation via Krylov-Subspace Algorithms (RWF), pp. 195–200.
DAC-1999-KamonMMSW #3d #analysis #modelling: Interconnect Analysis: From 3-D Structures to Circuit Models (MK, NAM, YM, LMS, JW), pp. 910–914.
DAC-1999-LiuPS #analysis: Model Order-Reduction of RC(L) Interconnect Including Variational Analysis (YL, LTP, AJS), pp. 201–206.
DAC-1999-LiWW #approach #equation #generative #modelling #performance: An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect (JRL, FW, JW), pp. 1–6.
DAC-1999-YimK #design: Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design (JSY, CMK), pp. 485–490.
DATE-1999-FeldmanKL #modelling #performance: Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics (PF, SK, DEL), pp. 418–417.
DATE-1999-RenovellPFZ #configuration management #interface #logic #testing: Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s (MR, JMP, JF, YZ), pp. 618–622.
DATE-1999-ShinKK #bound #multi #testing: At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks (JS, HK, SK), p. 473–?.
DATE-1999-ToulouseBLN #3d #modelling #performance: Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts (AT, DB, CL, PN), pp. 576–580.
DATE-1999-WangYK #distributed #estimation: Coupled Noise Estimation for Distributed RC Interconnect Model (JMW, QY, ESK), pp. 664–668.
UML-1999-AndradeF #contract: Interconnecting Objects Via Contracts (LFA, JLF), pp. 566–583.
SAC-1999-HarwoodS #low cost #network: A Method of Trading Diameter for Reduced Degree to Construct Low Cost Interconnection Networks (AH, HS), pp. 474–480.
HPCA-1999-PlaatBH #difference #latency #parallel #scalability: Sensitivity of Parallel Applications to Large Differences in Bandwidth and Latency in Two-Layer Interconnects (AP, HEB, RFHH), pp. 244–253.
DAC-1998-KrauterM #analysis #layout: Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis (BK, SM), pp. 303–308.
DAC-1998-LiuPS #modelling #named #order: ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models (YL, LTP, AJS), pp. 469–472.
DAC-1998-MarquesKWS #3d #modelling #performance: A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects (NAM, MK, JW, LMS), pp. 297–302.
DAC-1998-MassoudMBW #layout: Layout Techniques for Minimizing On-Chip Interconnect Self Inductance (YM, SSM, TB, JW), pp. 566–571.
DATE-1998-GasteierGM #communication #generative #synthesis: Generation of Interconnect Topologies for Communication Synthesis (MG, MG, MM), pp. 36–42.
DATE-1998-KahngMSS: Interconnect Tuning Strategies for High-Performance Ics (ABK, SM, ES, RS), pp. 471–478.
DATE-1998-MarquesKWS #3d #algorithm #modelling #order #performance #reduction: An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models (NAM, MK, JW, LMS), pp. 538–543.
DATE-1998-NordholzGTONAW #testing: Core Interconnect Testing Hazards (PN, HG, DT, JO, DN, UA, TWW), pp. 953–954.
DATE-1998-ShaoC #approximate #design #using: MCM Interconnect Design Using Two-Pole Approximation (JS, RMMC), pp. 544–548.
STOC-1998-ColeMHMRSSV #multi #network #protocol #random: Randomized Protocols for Low Congestion Circuit Routing in Multistage Interconnection Networks (RC, BMM, FMadH, MM, AWR, KS, RKS, BV), pp. 378–388.
HPCA-1998-KatevenisSS: Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch (MK, DNS, ES), pp. 47–56.
DAC-1997-DengiR #2d #modelling: Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling (EAD, RAR), pp. 127–132.
DAC-1997-ElfadelL #modelling #network: Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks (IME, DDL), pp. 28–33.
DAC-1997-NaborsFCK #modelling: Lumped Interconnect Models Via Gaussian Quadrature (KN, TTF, HWC, KSK), pp. 40–45.
EDTC-1997-Kristof #architecture #bound #effectiveness #idea #self #testing: Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections (AK), p. 630.
EDTC-1997-KunduG #analysis: Inductance analysis of on-chip interconnects [deep submicron CMOS] (SK, UG), pp. 252–255.
EDTC-1997-PomeranzR97a #finite #on the #state machine #testing: On the use of reset to increase the testability of interconnected finite-state machines (IP, SMR), pp. 554–559.
EDTC-1997-SousaC: Improved diagnosis of realistic interconnect shorts (JTdS, PYKC), pp. 501–505.
SAC-1997-ChoiK #multi #network: Hierarchical multistage interconnection network for shared-memory multiprocessor system (ChC, SCK), pp. 468–472.
HPCA-1997-DaoYD #architecture #communication #multi #network: Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks (BVD, SY, JD), pp. 343–352.
HPCA-1997-YuanMG #algorithm #distributed #multi #network: Distributed Path Reservation Algorithms for Multiplexed All-Optical Interconnection Networks (XY, RGM, RG), pp. 38–47.
DAC-1996-DartuTP #megamodelling #simulation: RC-Interconnect Macromodels for Timing Simulation (FD, BT, LTP), pp. 544–547.
DAC-1996-EliasM #modelling #scalability: Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency (PJHE, NPvdM), pp. 764–769.
DAC-1996-KahngM #analysis: Analysis of RC Interconnections Under Ramp Input (ABK, SM), pp. 533–538.
DAC-1996-KamonM #modelling: Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF Converter (MK, SSM), pp. 2–7.
DAC-1996-Park: A New Complete Diagnosis Patterns for Wiring Interconnects (SP), pp. 203–208.
DAC-1996-SunDH #equation #geometry #independence #parametricity #performance #using: Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance (WS, WWMD, WHI), pp. 371–376.
DAC-1996-TengCRK #reliability: Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects (CCT, YKC, ER, SMK), pp. 752–757.
ICSM-1996-MancoridisH #clustering #graph #using: Recovering the Structure of Software Systems Using Tube Graph Interconnection Clustering (SM, RCH), p. 23–?.
SAC-1996-AbualiWS #algorithm #design #problem #search-based #set #using: Solving the subset interconnection design problem using genetic algorithms (FNA, RLW, DAS), pp. 299–304.
HPCA-1996-QiaoM #multi #network #on the #permutation: On the Multiplexing Degree Required to Embed Permutations in a Class of Networks with Direct Interconnects (CQ, YM), pp. 118–129.
DAC-1995-ChouKW #3d #approach #simulation #using: Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume Approach (MC, TK, JW), pp. 485–490.
DAC-1995-MenezesPP #optimisation: Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.
DAC-1995-SilveiraKW #3d #modelling #performance: Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures (LMS, MK, JW), pp. 376–380.
FSE-1995-FiadeiroM #composition #reuse: Interconnecting Formalisms: Supporting Modularity, Reuse and Incrementality (JLF, TSEM), pp. 72–80.
HPCA-1995-CappelloG #communication #network #performance #towards: Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection Network (FC, CG), pp. 44–53.
HPCA-1995-QiaoM #communication #latency #multi: Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems (CQ, RGM), pp. 34–43.
DAC-1994-HaqueEC #megamodelling #multi #simulation: A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line Interconnections (MH, AEZ, SC), pp. 628–633.
DAC-1994-KahngM #analysis #equation #using: Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model (ABK, SM), pp. 563–569.
DAC-1994-KuznarBZ #clustering #multi: Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect (RK, FB, BZ), pp. 238–243.
DAC-1994-Sapatnekar #optimisation: RC Interconnect Optimization Under the Elmore Delay Model (SSS), pp. 387–391.
DAC-1994-VittalM #design #using: Minimal Delay Interconnect Design Using Alphabetic Trees (AV, MMS), pp. 392–396.
EDAC-1994-Su #bound #random testing #testing: Random Testing of Interconnects in A Boundary Scan Environment (CS), pp. 226–231.
ICALP-1994-Upfal #formal method #network #on the #parallel: On the Theory of Interconnection Networks for Parallel Computers (EU), pp. 473–486.
DAC-1993-ChiproutN #evaluation #performance: Addressing High-Speed Interconnect Issues in Asymptotic Waveform Evaluation (EC, MSN), pp. 732–736.
DAC-1993-ChouCC #finite #modelling #performance #simulation #using: High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods (TYC, JC, ZJC), pp. 684–690.
DAC-1993-CongLZ #design #distributed: Performance-Driven Interconnect Design Based on Distributed RC Delay Model (JC, KSL, DZ), pp. 606–611.
DAC-1993-HaqueC #analysis #design #distributed #reliability: Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections (MH, SC), pp. 697–701.
SAC-1993-ZhengLP #network: Sparse Hypercube-Like Interconnection Networks (SQZ, SL, EKP), pp. 694–700.
DAC-1992-ChangCLLO #design #named #performance: IPDA: Interconnect Performance Design Assistant (NHC, KJC, JL, KL, SYO), pp. 472–477.
DAC-1992-ChiproutN #analysis #network: Generalized Moment-Matching Methods for Transient Analysis of Interconnect Networks (EC, MSN), pp. 201–206.
DAC-1992-FranzonSSBMM #generative #tool support: Tools to Aid in Wiring Rule Generation for High Speed Interconnects (PDF, SS, MBS, MB, SM, TM), pp. 466–471.
DAC-1992-LingKW #3d #approach #bound #simulation: A Boundary-Element Approach to Transient simulation of Three-Dimensional Integrated Circuit Interconnect (DDL, SK, JW), pp. 93–98.
DAC-1992-LinK #simulation: Transient Simulation of Lossy Interconnect (SL, ESK), pp. 81–86.
DAC-1992-RaghavanBR #named #performance #problem #simulation: AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems (VR, JEB, RAR), pp. 87–92.
DAC-1992-RoychowdhuryNP #linear #simulation: Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time (JSR, ARN, DOP), pp. 75–80.
DAC-1992-RuehliH #analysis #challenge: Challenges and Advances in Electrical Interconnect Analysis (AER, HH), pp. 460–465.
DAC-1991-MattesWBD: Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected Waves (HM, WW, GB, RD), pp. 567–572.
DAC-1991-OgawaIMIST #constraints #design: Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design (YO, TI, YM, TI, YS, RT), pp. 253–258.
DAC-1991-RaghavanR #analysis: A New Nonlinear Driver Model for Interconnect Analysis (VR, RAR), pp. 561–566.
DAC-1991-RatzlaffGP #agile #named: RICE: Rapid Interconnect Circuit Evaluator (CLR, NG, LTP), pp. 555–560.
DAC-1991-RoychowdhuryP #performance #simulation: Efficient Transient Simulation of Lossy Interconnect (JSR, DOP), pp. 740–745.
DAC-1990-LyEG #synthesis: A Generalized Interconnect Model for Data Path Synthesis (TAL, WLE, EFG), pp. 168–173.
DAC-1990-McCormickA #analysis: Waveform Moment Methods for Improved Interconnection Analysis (SPM, JA), pp. 406–412.
DAC-1990-PapachristouK #algorithm #linear #optimisation #scheduling: A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm (CAP, HK), pp. 77–83.
DAC-1989-GuraA: Average Interconnection Length and Interconnection Distribution Based on Rent’s Rule (CVG, JAA), pp. 574–577.
ICSE-1987-Perry #modelling: Software Interconnection Models (DEP), pp. 61–71.
GG-1986-BaileyC #grammarware #graph grammar #parallel #specification: Graph Grammar Based Specification of Interconnection Structures for Massively Parallel Computation (DAB, JEC), pp. 73–85.
DAC-1984-GeusRRW #analysis #named: IDA: Interconnect delay analysis for integrated circuits (AJdG, JBR, MR, GW), pp. 536–541.
DAC-1984-Ng #design: A symbolic-interconnect router for custom IC design (CHN), pp. 52–58.
DAC-1982-Heyns #algorithm: The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers (WH), pp. 113–120.
DAC-1982-Rivest: The “PI” (placement and interconnect) system (RLR), pp. 475–481.
ICALP-1982-GoguenM #implementation #persistent: Universal Realization, Persistent Interconnection and Implementation of Abstract Modules (JAG, JM), pp. 265–281.
DAC-1981-DeesS #performance: Performance of interconnection rip-up and reroute strategies (WADJ, RJSI), pp. 382–390.
DAC-1981-MalladiSV #automation: Automatic placement of rectangular blocks with the interconnection channels (RM, GS, AV), pp. 419–425.
DAC-1980-AltmanP #analysis #design: The SLIDE simulator: A facility for the design and analysis of computer interconnections (AHA, ACP), pp. 148–155.
ICSE-1979-BerryP #design #specification: The Use of a Module Interconnection Specification Capability in the SARA System Design Methodology (DMB, MH(P), pp. 294–307.
ICSE-1979-Tichy #development: Software Development Based on Module Interconnection (WFT), pp. 29–41.
DAC-1976-Rau #multi: A new philosophy for interconnection on multilayer boards (BRR), pp. 225–231.
DAC-1973-Hightower #problem #tutorial: The interconnection problem — a tutorial (DWH), pp. 1–21.
DAC-1973-Ruehli #design #logic: Electrical considerations in the computer aided design of logic circuit interconnections (AER), pp. 262–266.
DAC-1969-Wilson: A computer aided interconnection system (RWW), pp. 281–289.
DAC-1968-KlemetsmoMW #automation #process: Graphic display techniques in the automated interconnection process (RRK, GAM, AIW).
SHARE-1965-Frayne #problem: Three levels of the wiring interconnection problem (DKF).