BibSLEIGH corpus
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Open Knowledge
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Travelled to:
1 × USA
Collaborated with:
Talks about:
interconnect (1) power (1) petri (1) model (1) estim (1) delay (1) gate (1) net (1)

Person: Ashok K. Murugavel

DBLP DBLP: Murugavel:Ashok_K=

Contributed to:

DAC 20022002

Wrote 1 papers:

DAC-2002-MurugavelR #estimation #modelling #petri net
Petri net modeling of gate and interconnect delays for power estimation (AKM, NR), pp. 455–460.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.