Clock tree synthesis with pre-bond testability for 3D stacked IC designs
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Tak-Yung Kim, Taewhan Kim
Clock tree synthesis with pre-bond testability for 3D stacked IC designs
DAC, 2010.

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@inproceedings{DAC-2010-KimK,
	author        = "Tak-Yung Kim and Taewhan Kim",
	booktitle     = "{Proceedings of the 47th Design Automation Conference}",
	doi           = "10.1145/1837274.1837456",
	isbn          = "978-1-4503-0002-5",
	pages         = "723--728",
	publisher     = "{ACM}",
	title         = "{Clock tree synthesis with pre-bond testability for 3D stacked IC designs}",
	year          = 2010,
}

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