BibSLEIGH — Proceedings of the 47th Design Automation Conference

Sachin S. Sapatnekar
Proceedings of the 47th Design Automation Conference
DAC, 2010.

SYS

@proceedings{DAC-2010,
	acmid         = "1837274",
	address       = "Anaheim, California, USA",
	editor        = "Sachin S. Sapatnekar",
	isbn          = "978-1-4503-0002-5",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 47th Design Automation Conference}",
	year          = 2010,
}

Contents (182 items)

DAC-2010-PuriJJJRRS #challenge: EDA challenges and options: investing for the future (RP, WHJ, RJ, AJ, JMR, WCR, LS), pp. 1–2.
DAC-2010-KeshavaHP #challenge #how #validation: Post-silicon validation challenges: how EDA and academia can help (JK, NH, CP), pp. 3–7.
DAC-2010-GoodenoughA #design: Post-silicon is too late avoiding the $50 million paperweight starts with validated designs (JG, RA), pp. 8–11.
DAC-2010-MitraSN #challenge #validation: Post-silicon validation opportunities, challenges and recent advances (SM, SAS, NN), pp. 12–17.
DAC-2010-HsuPH #approach #data flow #modelling #physics #simulation: A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layer (CJH, JLP, FJH), pp. 18–23.
DAC-2010-BombieriFP #abstraction #embedded: Abstraction of RTL IPs into embedded software (NB, FF, GP), pp. 24–29.
DAC-2010-SirowyHV #online: Online SystemC emulation acceleration (SS, CH, FV), pp. 30–35.
DAC-2010-KuangB #latency #named: LATA: a latency and throughput-aware packet processing system (JK, LNB), pp. 36–41.
DAC-2010-ZitterellS #approach #energy #online #probability #realtime #scheduling: A probabilistic and energy-efficient scheduling approach for online application in real-time systems (TZ, CS), pp. 42–47.
DAC-2010-JuHRC #analysis #multi #source code: Timing analysis of esterel programs on general-purpose multiprocessors (LJ, BKH, AR, SC), pp. 48–51.
DAC-2010-LuoWH #effectiveness #gpu #implementation: An effective GPU implementation of breadth-first search (LL, MDFW, WmWH), pp. 52–55.
DAC-2010-NowrozCR #monitoring: Thermal monitoring of real processors: techniques for sensor allocation and full characterization (ANN, RC, SR), pp. 56–61.
DAC-2010-CochranR #consistency #detection #predict #runtime: Consistent runtime thermal prediction and control through workload phase detection (RC, SR), pp. 62–67.
DAC-2010-ZhangS #adaptation #performance: Adaptive and autonomous thermal tracking for high performance computing systems (YZ, AS), pp. 68–73.
DAC-2010-GuthausWR #linear #optimisation #programming: Non-uniform clock mesh optimization with linear programming buffer insertion (MRG, GW, RR), pp. 74–79.
DAC-2010-ShihC #independence #performance #synthesis: Fast timing-model independent buffered clock-tree synthesis (XWS, YWC), pp. 80–85.
DAC-2010-ChenDC #synthesis: Clock tree synthesis under aggressive buffer insertion (YYC, CD, DC), pp. 86–89.
DAC-2010-LiuZYCSZ #design: Global routing and track assignment for flip-chip designs (XL, YZ, GKY, CC, JS, XZ), pp. 90–93.
DAC-2010-NahirZGHACBFBK #validation #verification: Bridging pre-silicon verification and post-silicon validation (AN, AZ, RG, AJH, MA, AC, BB, HF, VB, SK), pp. 94–95.
DAC-2010-BertinGB #compilation: Compilation and virtualization in the HiPEAC vision (CB, CG, KDB), pp. 96–101.
DAC-2010-CohenR #compilation #embedded #manycore: Processor virtualization and split compilation for heterogeneous multicore embedded systems (AC, ER), pp. 102–107.
DAC-2010-LeeSC #data access #fine-grained #mobile: Fine-grained I/O access control based on Xen virtualization for 3G/4G mobile devices (SML, SBS, JDC), pp. 108–113.
DAC-2010-Fornaeus: Device hypervisors (JF), pp. 114–119.
DAC-2010-MarianiBPJZS #design #multi: A correlation-based design space exploration methodology for multi-processor systems-on-chip (GM, AB, GP, JJ, VZ, CS), pp. 120–125.
DAC-2010-ZhaoDX #3d #cost analysis #design #manycore: Cost-aware three-dimensional (3D) many-core multiprocessor design (JZ, XD, YX), pp. 126–131.
DAC-2010-YuP #clustering #manycore #memory management #platform: Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms (CY, PP), pp. 132–137.
DAC-2010-NalamBMC #design #optimisation #prototype: Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers (SN, MB, KM, BHC), pp. 138–143.
DAC-2010-OzdemirPDMLC #3d #architecture #parametricity: Quantifying and coping with parametric variations in 3D-stacked microarchitectures (SO, YP, AD, GM, GHL, ANC), pp. 144–149.
DAC-2010-WuSDDXDL #3d #integration: Cost-driven 3D integration with interconnect layers (XW, GS, XD, RD, YX, CRD, JL), pp. 150–155.
DAC-2010-ZhangL #manycore #network: A multilayer nanophotonic interconnection network for on-chip many-core communications (XZ, AL), pp. 156–161.
DAC-2010-YoonCPC #analysis #comparative #multi #network #physics: Virtual channels vs. multiple physical networks: a comparative analysis (YJY, NC, MP, LPC), pp. 162–165.
DAC-2010-ModarressiST #architecture #configuration management #network #performance: An efficient dynamically reconfigurable on-chip network architecture (MM, HSA, AT), pp. 166–169.
DAC-2010-PigorschS #preprocessor #satisfiability #using: An AIG-Based QBF-solver using SAT for preprocessing (FP, CS), pp. 170–175.
DAC-2010-ThalmaierNWSBK #induction #invariant #satisfiability: Analyzing k-step induction to compute invariants for SAT-based property checking (MT, MDN, MW, DS, JB, WK), pp. 176–181.
DAC-2010-ChocklerKP #model checking: Coverage in interpolation-based model checking (HC, DK, MP), pp. 182–187.
DAC-2010-Coudert #algorithm #performance #verification: An efficient algorithm to verify generalized false paths (OC), pp. 188–193.
DAC-2010-WuDL #approach #integer #parallel #programming: A parallel integer programming approach to global routing (THW, AD, JTL), pp. 194–199.
DAC-2010-LiuKLC #bound #concurrent #multi #thread: Multi-threaded collision-aware global routing with bounded-length maze routing (WHL, WCK, YLL, KYC), pp. 200–205.
DAC-2010-YanC: Two-sided single-detour untangling for bus routing (JTY, ZWC), pp. 206–211.
DAC-2010-KongMYW #algorithm: An optimal algorithm for finding disjoint rectangles and its application to PCB routing (HK, QM, TY, MDFW), pp. 212–217.
DAC-2010-NSRKALPST #problem #question #variability: Who solves the variability problem? (NN, JCR, JK, RCA, CL, VP, AJS, ST), pp. 218–219.
DAC-2010-RiedelHWSAM #biology: Joint DAC/IWBDA special session engineering biology: fundamentals and applications (MR, SH, RW, PS, JCA, RMM), pp. 220–221.
DAC-2010-WeiMP #hardware #security: Gate-level characterization: foundations and hardware security applications (SW, SM, MP), pp. 222–227.
DAC-2010-LishernessC #fault #injection #named: SCEMIT: a systemc error and mutation injection tool (PL, KT(C), pp. 228–233.
DAC-2010-GlassLHT #analysis #reliability #scalability #towards: Towards scalable system-level reliability analysis (MG, ML, CH, JT), pp. 234–239.
DAC-2010-HelinskiAP #evaluation #metric #physics #quality: Quality metric evaluation of a physical unclonable function derived from an IC’s power distribution system (RH, DA, JP), pp. 240–243.
DAC-2010-ObergHITSK #analysis #data flow: Theoretical analysis of gate level information flow tracking (JO, WH, AI, MT, TS, RK), pp. 244–247.
DAC-2010-NovoLFRC #data flow #finite #precise: Exploiting finite precision information to guide data-flow mapping (DN, ML, RF, PR, FC), pp. 248–253.
DAC-2010-KinsmanN #algorithm #design #hardware #robust: Robust design methods for hardware accelerators for iterative algorithms in scientific computing (ABK, NN), pp. 254–257.
DAC-2010-JouWLCJ #architecture #design #generative #modelling #multi: New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model (JMJ, SSW, YLL, CC, YLJ), pp. 258–261.
DAC-2010-ZhangLR: Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference (WZ, XL, RAR), pp. 262–267.
DAC-2010-SilvaPS #analysis #modelling #parametricity: Speedpath analysis under parametric timing models (LGeS, JRP, LMS), pp. 268–273.
DAC-2010-XieDS: Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations (LX, AD, KKS), pp. 274–279.
DAC-2010-ChuangKSC #optimisation: Pulsed-latch aware placement for timing-integrity optimization (YLC, SK, YS, YWC), pp. 280–285.
DAC-2010-ChoRXP #network #using: History-based VLSI legalization using network flow (MC, HR, HX, RP), pp. 286–291.
DAC-2010-LinLHC #bound #constraints: Performance-driven analog placement considering boundary constraint (CWL, JML, CPH, SJC), pp. 292–297.
DAC-2010-BansalRYJLMMR #3d #question: 3-D stacked die: now or future? (SB, JCR, AY, MSJ, LCL, PM, PM, RR), pp. 298–299.
DAC-2010-MicheliSMBAP #network #research: Networks on Chips: from research to products (GDM, CS, SM, LB, FA, AP), pp. 300–305.
DAC-2010-GoossensH #evolution #network: The aethereal network on chip after ten years: goals, evolution, lessons, and future (KG, AH), pp. 306–311.
DAC-2010-Mathewson #evolution #how: The evolution of SOC interconnect and how NOC fits within it (BM), pp. 312–313.
DAC-2010-NurvitadhiHLK #automation #parallel #pipes and filters #specification #synthesis #thread #transaction: Automatic multithreaded pipeline synthesis from transactional datapath specifications (EN, JCH, SLL, TK), pp. 314–319.
DAC-2010-NadakuditiM #cost analysis #on the: On the costs and benefits of stochasticity in stream processing (RRN, ILM), pp. 320–325.
DAC-2010-HuangX #performance #process #scheduling: Performance yield-driven task allocation and scheduling for MPSoCs under process variation (LH, QX), pp. 326–331.
DAC-2010-SchranzhoferPCTC #analysis #manycore #modelling #resource management #worst-case: Worst-case response time analysis of resource access models in multi-core systems (AS, RP, JJC, LT, MC), pp. 332–337.
DAC-2010-LiaoYB #performance: A new IP lookup cache for high performance IP routers (GL, HY, LNB), pp. 338–343.
DAC-2010-LiangM #reuse #using: Instruction cache locking using temporal reuse profile (YL, TM), pp. 344–349.
DAC-2010-HuXTHQS #embedded #migration #process: Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation (JH, CJX, WCT, YH, MQ, EHMS), pp. 350–355.
DAC-2010-HaquePJP #approach #embedded #named #performance #policy #simulation: SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy (MSH, JP, AJ, SP), pp. 356–361.
DAC-2010-WohlWNG: Fully X-tolerant, very high scan compression (PW, JAW, FN, EG), pp. 362–367.
DAC-2010-ParkBWM #debugging #graph #locality #named #using: BLoG: post-silicon bug localization in processors using bug localization graphs (SBP, AB, HW, SM), pp. 368–373.
DAC-2010-CallegariDWA #classification #learning #using: Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch (NC, DGD, LCW, MSA), pp. 374–379.
DAC-2010-KochteSWZ #fault #manycore #performance #simulation: Efficient fault simulation on many-core processors (MAK, MS, HJW, CGZ), pp. 380–385.
DAC-2010-XieD #predict #variability: Representative path selection for post-silicon timing prediction under variability (LX, AD), pp. 386–391.
DAC-2010-GongYSKRH #constraints #estimation #named #parametricity #performance: QuickYield: an efficient global-search based parametric yield estimation with performance constraints (FG, HY, YS, DK, JR, LH), pp. 392–397.
DAC-2010-LinL #graph: Double patterning lithography aware gridless detailed routing with innovative conflict graph (YHL, YLL), pp. 398–403.
DAC-2010-Agarwal #composition: Frequency domain decomposition of layouts for double dipole lithography (KA), pp. 404–407.
DAC-2010-BanP #layout #modelling #optimisation #robust: Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography (YB, DZP), pp. 408–411.
DAC-2010-KuehlmannCCCGGLS #design #in the cloud #question: Does IC design have a future in the clouds? (AK, RC, JC, JC, SG, RG, PL, DS), pp. 412–414.
DAC-2010-BondD #automation #design #modelling: Automated compact dynamical modeling: an enabling tool for analog designers (BNB, LD), pp. 415–420.
DAC-2010-KundertC #functional #modelling #verification: Model-based functional verification (KSK, HC), pp. 421–424.
DAC-2010-HorowitzJLLLM #analysis #equivalence #modelling: Fortifying analog models with equivalence checking and coverage analysis (MH, MJ, FL, SL, BL, JM), pp. 425–430.
DAC-2010-IhrigMJ #automation #design #manycore #modelling: Automated modeling and emulation of interconnect designs for many-core chip multiprocessors (CJI, RGM, AKJ), pp. 431–436.
DAC-2010-KahngLSR #optimisation: Trace-driven optimization of networks-on-chip configurations (ABK, BL, KS, RSR), pp. 437–442.
DAC-2010-CongLR #concurrent #named: ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip (JC, CL, GR), pp. 443–448.
DAC-2010-HuangCKT #named #network #predict: NTPT: on the end-to-end traffic prediction in the on-chip networks (YSCH, KCKC, CTK, SYT), pp. 449–452.
DAC-2010-JangP #design #performance: Application-aware NoC design for efficient SDRAM access (WJ, DZP), pp. 453–456.
DAC-2010-ElizehN #embedded #memory management: Embedded memory binding in FPGAs (KE, NN), pp. 457–462.
DAC-2010-TanWALCPA #architecture #multi: RAMP gold: an FPGA-based architecture simulator for multiprocessors (ZT, AW, RA, YL, HC, DAP, KA), pp. 463–468.
DAC-2010-JoseHMH #robust: Rewiring for robustness (MJ, YH, RM, LH), pp. 469–474.
DAC-2010-GaoYWY #analysis #correlation #estimation #performance #statistics: Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis (MG, ZY, YW, ZY), pp. 475–480.
DAC-2010-ShenTX #algorithm #analysis #correlation #linear #power management #statistics: A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation (RS, SXDT, JX), pp. 481–486.
DAC-2010-SeomunSS #implementation #power management #synthesis: Synthesis and implementation of active mode power gating circuits (JS, IS, YS), pp. 487–492.
DAC-2010-YuVH #adaptation #multi #realtime #scheduling: Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems (HY, BV, YH), pp. 493–498.
DAC-2010-LaiJW #abstraction #learning #named: BooM: a decision procedure for boolean matching with abstraction and dynamic learning (CFL, JHRJ, KHW), pp. 499–504.
DAC-2010-ChenW: Node addition and removal in the presence of don’t cares (YCC, CYW), pp. 505–510.
DAC-2010-YangLW #complexity #fault #named: ECR: a low complexity generalized error cancellation rewiring scheme (XY, TKL, YLW), pp. 511–516.
DAC-2010-CongM #reliability: LUT-based FPGA technology mapping for reliability (JC, KM), pp. 517–522.
DAC-2010-NsBNPSGB #design #future of #power management #question #what: What’s cool for the future of ultra low power designs? (NN, JB, KN, VP, TS, AG, SB), pp. 523–524.
DAC-2010-ThomptoH #fault tolerance #verification: Verification for fault tolerance of the IBM system z microprocessor (BWT, BH), pp. 525–530.
DAC-2010-Miskov-ZivanovM #analysis #formal method #modelling #reasoning #reliability: Formal modeling and reasoning for reliability analysis (NMZ, DM), pp. 531–536.
DAC-2010-ConstantinidesA #debugging #testing #using: Using introspective software-based testing for post-silicon debug and repair (KC, TMA), pp. 537–542.
DAC-2010-HePKYALC #energy #named #throughput: Xetal-Pro: an ultra-low energy and high throughput SIMD processor (YH, YP, RPK, ZY, AAA, SML, HC), pp. 543–548.
DAC-2010-IosifidisMMGBSC #automation #framework #memory management #optimisation #parallel #platform: A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms (YI, AM, SM, EdG, AB, DS, FC), pp. 549–554.
DAC-2010-ChippaMRRC #algorithm #design #energy #hardware #performance #scalability: Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency (VKC, DM, AR, KR, STC), pp. 555–560.
DAC-2010-YeL #modelling #optimisation #parallel #performance #runtime #simulation: Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation (XY, PL), pp. 561–566.
DAC-2010-ZhangLH #analysis: Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis (YZ, PL, GMH), pp. 567–572.
DAC-2010-LiuYT #algorithm #analysis #performance #robust #scalability: A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs (XL, HY, SXDT), pp. 573–578.
DAC-2010-GeMQ #distributed #manycore #migration: Distributed task migration for thermal management in many-core systems (YG, PM, QQ), pp. 579–584.
DAC-2010-ZhangC #embedded: Thermal aware task sequencing on embedded processors (SZ, KSC), pp. 585–590.
DAC-2010-LongM #framework #optimisation: A framework for optimizing thermoelectric active cooling systems (JL, SOM), pp. 591–596.
DAC-2010-GuptaKKS #benchmark #heuristic #metric #named: Eyecharts: constructive benchmarking of gate sizing heuristics (PG, ABK, AK, PS), pp. 597–602.
DAC-2010-JindalAHLNW #detection #logic: Detecting tangled logic structures in VLSI netlists (TJ, CJA, JH, ZL, GJN, CBW), pp. 603–608.
DAC-2010-AltunR: Lattice-based computation of Boolean functions (MA, MDR), pp. 609–612.
DAC-2010-ThongN #algorithm #constant #multi #novel: A novel optimal single constant multiplication algorithm (JT, NN), pp. 613–616.
DAC-2010-ChouMM #design #embedded #experience: Find your flow: increasing flow experience by designing “human” embedded systems (CLC, AMM, RM), pp. 619–620.
DAC-2010-DeOrioB #automation #design #network #social: Electronic design automation for social networks (AD, VB), pp. 621–622.
DAC-2010-MirhoseiniAK #realtime: Real time emulations: foundation and applications (AM, YA, FK), pp. 623–624.
DAC-2010-Ababei #design #modelling #network #optimisation #using: Network on chip design and optimization using specialized influence models (CA), pp. 625–626.
DAC-2010-TruongB #architecture #design #manycore #modelling: Circuit modeling for practical many-core architecture design exploration (DT, BMB), pp. 627–628.
DAC-2010-Koushanfar #hybrid #network #power management: Hierarchical hybrid power supply networks (FK), pp. 629–630.
DAC-2010-FujitaYLCAW #power management: Detachable nano-carbon chip with ultra low power (SF, SY, DL, XC, DA, HSPW), pp. 631–632.
DAC-2010-Potkonjak #synthesis #tool support #using: Synthesis of trustable ICs using untrusted CAD tools (MP), pp. 633–634.
DAC-2010-ZhaoC: Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips (YZ, KC), pp. 635–640.
DAC-2010-LinC #design: Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips (CCYL, YWC), pp. 641–646.
DAC-2010-WilleSD: Reducing the number of lines in reversible circuits (RW, MS, RD), pp. 647–652.
DAC-2010-GolubitskyFM #synthesis: Synthesis of the optimal 4-bit reversible circuits (OG, SMF, DM), pp. 653–656.
DAC-2010-XieNXZLWYWL #analysis #fault: Crosstalk noise and bit error rate analysis for optical network-on-chip (YX, MN, JX, WZ, QL, XW, YY, XW, WL), pp. 657–660.
DAC-2010-FengZ #analysis #grid #parallel #power management #robust: Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis (ZF, ZZ), pp. 661–666.
DAC-2010-El-MoselhyD #probability: Stochastic dominant singular vectors method for variation-aware extraction (TAEM, LD), pp. 667–672.
DAC-2010-JoshiSTASB #modelling: Closed-form modeling of layout-dependent mechanical stress (VJ, VS, AT, KA, DS, DB), pp. 673–678.
DAC-2010-LefteriuM #generative #modelling #parametricity: Generating parametric models from tabulated data (SL, JM), pp. 679–682.
DAC-2010-WangLPW #modelling #multi #named: MFTI: matrix-format tangential interpolation for modeling multi-port systems (YW, CUL, GKHP, NW), pp. 683–686.
DAC-2010-XiaoSH #algorithm: A universal state-of-charge algorithm for batteries (BX, YS, LH), pp. 687–692.
DAC-2010-PashaDS #architecture #generative #power management: A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking (MAP, SD, OS), pp. 693–698.
DAC-2010-CabeQS #power management: Stacking SRAM banks for ultra low power standby mode operation (ACC, ZQ, MRS), pp. 699–704.
DAC-2010-WangM #approximate #named #realtime #scalability #using: PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme (WW, PM), pp. 705–710.
DAC-2010-ChellappaNYHVCCC #variability: In-situ characterization and extraction of SRAM variability (SC, JN, XY, NDH, JV, MC, YC, LTC), pp. 711–716.
DAC-2010-ZuberDM #analysis #approach #statistics: A holistic approach for statistical SRAM analysis (PZ, PD, MM), pp. 717–722.
DAC-2010-KimK #3d #design #synthesis #testing: Clock tree synthesis with pre-bond testability for 3D stacked IC designs (TYK, TK), pp. 723–728.
DAC-2010-KaoCTC #detection #performance: An efficient phase detector connection structure for the skew synchronization system (YCK, HMC, KTT, SCC), pp. 729–734.
DAC-2010-HarmsCDHUWY #design #experience #question #what: What will make your next design experience a much better one? (TH, JAC, RD, RAH, DU, GW, JY), p. 730.
DAC-2010-RajkumarLSS #cyber-physical: Cyber-physical systems: the next computing revolution (RR, IL, LS, JAS), pp. 731–736.
DAC-2010-Lee #continuation: CPS foundations (EAL), pp. 737–742.
DAC-2010-LeeS #physics: Medical cyber physical systems (IL, OS), pp. 743–748.
DAC-2010-KleisslA #cyber-physical #energy: Cyber-physical energy systems: focus on smart buildings (JK, YA), pp. 749–754.
DAC-2010-LiFS #mining #scalability #specification #verification: Scalable specification mining for verification and diagnosis (WL, AF, SAS), pp. 755–760.
DAC-2010-WangZD #distributed #logic #parallel #simulation: Distributed time, conservative parallel logic simulation on GPUs (BDW, YZ, YD), pp. 761–766.
DAC-2010-LimKH #functional #generative #modelling #performance: An efficient test vector generation for checking analog/mixed-signal functional models (BL, JK, MAH), pp. 767–772.
DAC-2010-HazraMDPBG #architecture #modelling #verification: Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent (AH, SM, PD, AP, DB, KG), pp. 773–776.
DAC-2010-FayyaziK #performance #simulation: Efficient simulation of oscillatory combinational loops (MF, LK), pp. 777–780.
DAC-2010-BeeceXVZL #parametricity: Transistor sizing of custom high-performance digital circuits with parametric yield considerations (DKB, JX, CV, VZ, YL), pp. 781–786.
DAC-2010-TangZBM #analysis #simulation #statistics: RDE-based transistor-level gate simulation for statistical static timing analysis (QT, AZ, MB, NvdM), pp. 787–792.
DAC-2010-VeetilCSB #monte carlo #performance #resource management: Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization (VV, YHC, DS, DB), pp. 793–798.
DAC-2010-HsuLML #analysis #flexibility: Static timing analysis for flexible TFT circuits (CHH, CL, EHM, JCML), pp. 799–802.
DAC-2010-YangALLP #3d #analysis #layout #optimisation: TSV stress aware timing analysis with applications to 3D-IC layout optimization (JSY, KA, YJL, SKL, DZP), pp. 803–806.
DAC-2010-DhimanMR #modelling #online #predict #using: A system for online power prediction in virtualized environments using Gaussian mixture models (GD, KM, TR), pp. 807–812.
DAC-2010-ChenXDM #manycore #modelling #performance: Performance and power modeling in a multi-programmed multi-core environment (XC, CX, RPD, ZMM), pp. 813–818.
DAC-2010-SridharanM #embedded #power management #realtime #reliability: Reliability aware power management for dual-processor real-time embedded systems (RS, RNM), pp. 819–824.
DAC-2010-KahngKKS #design #power management: Recovery-driven design: a power minimization methodology for error-tolerant processor modules (ABK, SK, RK, JS), pp. 825–830.
DAC-2010-ZengYFL #analysis #delivery #network #optimisation #power management #trade-off: Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation (ZZ, XY, ZF, PL), pp. 831–836.
DAC-2010-XiongW #algorithm #constraints #grid #linear #performance #power management #verification: An efficient dual algorithm for vectorless power grid verification under linear current constraints (XX, JW), pp. 837–842.
DAC-2010-ZhaoGFH #optimisation #parallel: Parallel hierarchical cross entropy optimization for on-chip decap budgeting (XZ, YG, ZF, SH), pp. 843–848.
DAC-2010-QiWCWBCS #design: SRAM-based NBTI/PBTI sensor system design (ZQ, JW, ACC, SNW, TNB, BHC, MRS), pp. 849–852.
DAC-2010-FonsecaDBGPVB #analysis #reliability #simulation #statistics: A statistical simulation method for reliability analysis of SRAM core-cells (RAF, LD, AB, PG, SP, AV, NB), pp. 853–856.
DAC-2010-GajskiAS #question #synthesis #what: What input-language is the best choice for high level synthesis (HLS)? (DG, TMA, SS), pp. 857–858.
DAC-2010-ShanbhagAKJ #probability: Stochastic computation (NRS, RAA, RK, DLJ), pp. 859–864.
DAC-2010-ChakradharR #hardware #parallel: Best-effort computing: re-thinking parallel software and hardware (STC, AR), pp. 865–870.
DAC-2010-Breuer #bound #hardware: Hardware that produces bounded rather than exact results (MAB), pp. 871–876.
DAC-2010-NiuCXX #process: Impact of process variations on emerging memristor (DN, YC, CX, YX), pp. 877–882.
DAC-2010-TanachutiwatLWS #configuration management #logic #multi: Reconfigurable multi-function logic based on graphene P-N junctions (ST, JUL, WW, CYS), pp. 883–888.
DAC-2010-ZhangBPLWMM #correlation: Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement (JZ, SB, NP, AL, HSPW, GDM, SM), pp. 889–892.
DAC-2010-DadgourHSB #analysis #design #energy #logic #using: Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS (HFD, MMH, CS, KB), pp. 893–896.
DAC-2010-ZhangCTL #modelling #multi #performance #scalability #towards: Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression (WZ, THC, MYT, XL), pp. 897–902.
DAC-2010-KuoCTCL #approach #behaviour: Behavior-level yield enhancement approach for large-scaled analog circuits (CCK, YLC, ICT, LYC, CNJL), pp. 903–908.
DAC-2010-LiuYHSK #generative #optimisation: Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances (YL, MY, KH, TS, YK), pp. 909–912.
DAC-2010-SingheeC: Pareto sampling: choosing the right weights by derivative pursuit (AS, PC), pp. 913–916.
DAC-2010-ChangHKCW #3d #fault: An error tolerance scheme for 3D CMOS imagers (HMC, JLH, DMK, KT(C, CWW), pp. 917–922.
DAC-2010-WangCW #identification #performance: Fast identification of operating current for toggle MRAM by spiral search (SHW, CYC, CWW), pp. 923–928.
DAC-2010-YinL #low cost #monitoring: Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs (LY, PL), pp. 929–934.
DAC-2010-JohnR #smarttech: Smart phone power (JJ, CR), pp. 935–936.
DAC-2010-Hiskens #grid #question #smarttech #what: What’s smart about the smart grid? (IAH), pp. 937–939.
DAC-2010-Chiprout #power management: On-die power grids: the missing link (EC), pp. 940–945.

Sachin S. SapatnekarProceedings of the 47th Design Automation ConferenceDAC, 2010.

Contents (182 items)

Sachin S. Sapatnekar
Proceedings of the 47th Design Automation Conference
DAC, 2010.