Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms
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Carlos Flores Fajardo, Zhen Fang, Ravi Iyer, German Fabila Garcia, Seung Eun Lee, Li Zhao
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms
DAC, 2011.

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@inproceedings{DAC-2011-FajardoFIGLZ,
	author        = "Carlos Flores Fajardo and Zhen Fang and Ravi Iyer and German Fabila Garcia and Seung Eun Lee and Li Zhao",
	booktitle     = "{Proceedings of the 48th Design Automation Conference}",
	doi           = "10.1145/2024724.2024938",
	isbn          = "978-1-4503-0636-2",
	pages         = "966--971",
	publisher     = "{ACM}",
	title         = "{Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms}",
	year          = 2011,
}

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