Stem sram$ (all stems)

95 papers:

DAC-2015-RakshitWLGM #design #power management #robust

Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design (JR, RW, KTL, JG, KM), p. 6.

DAC-2015-XieLXCJJ

Jump test for metallic CNTs in CNFET-based SRAM (FX, XL, QX, KC, NJ, LJ), p. 6.

DATE-2015-AwanoHS #named #performance #probability

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell (HA, MH, TS), pp. 549–554.

DATE-2015-GoudVRR #design #robust #symmetry

Asymmetric underlapped FinFET based robust SRAM design at 7nm node (AAG, RV, AR, KR), pp. 659–664.

DATE-2015-KarageorgosSRRT #multi #variability

Impact of interconnect multiple-patterning variability on SRAMs (IK, MS, PR, JR, ZT, DV, RB, SS, WD), pp. 609–612.

DATE-2015-LiLZGSSZCLY #energy #performance

An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes (HL, YL, QZ, YG, XS, GS, CZ, MFC, RL, HY), pp. 7–12.

DATE-2015-ShutoYS #architecture #case study #comparative #using

Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology (YS, SY, SS), pp. 866–871.

DAC-2014-HameedBH #architecture #latency #novel

Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture (FH, LB, JH), p. 6.

DAC-2014-KiamehrOTN #analysis #approach #fault

Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach (SK, THO, MBT, SRN), p. 6.

DAC-2014-RaoEST #multi #using

Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes (PMBR, ME, RS, MBT), p. 6.

DAC-2014-TsaiCYYHCCC #energy #using

Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination (HJT, CCC, KHY, TCY, LYH, CHC, MFC, TFC), p. 6.

DATE-2014-AlordaCB #embedded #power management #reliability

Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications (BA, CC, SAB), pp. 1–6.

DATE-2014-JunsangsriLH #concurrent #detection #hybrid

A hybrid non-volatile SRAM cell with concurrent SEU detection and correction (PJ, FL, JH), pp. 1–4.

DATE-2014-KhanAHKKRC #analysis #bias

Bias Temperature Instability analysis of FinFET based SRAM cells (SK, IA, SH, HK, BK, PR, FC), pp. 1–6.

DATE-2014-RanaC #analysis #named #reduction #scalability #simulation

SSFB: A highly-efficient and scalable simulation reduction technique for SRAM yield analysis (MR, RC), pp. 1–6.

DATE-2014-SunMSPL #design #power management #robust

A low power and robust carbon nanotube 6T SRAM design with metallic tolerance (LS, JM, RAS, DKP, ZL), pp. 1–4.

DATE-2014-TsaiCCC #3d #configuration management #memory management #multi

Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs (MLT, YJC, YTC, RHC), pp. 1–6.

DAC-2013-CalimeraMP #constraints #energy #fault #scheduling

Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints (AC, EM, MP), p. 6.

DAC-2013-ZhengHB #array #embedded #named #physics #robust

RESP: a robust physical unclonable function retrofitted into embedded SRAM array (YZ, MH, SB), p. 9.

DATE-2013-BoleyCAC #analysis #estimation #performance

Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN (JB, VC, RCA, BHC), pp. 1819–1824.

DATE-2013-HameedBH #adaptation #multi

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores (FH, LB, JH), pp. 77–82.

DATE-2013-PouyanAMR #adaptation #configuration management #design #implementation

Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches (PP, EA, FM, AR), pp. 1303–1306.

DATE-2013-YuehCM #architecture #quality

Perceptual quality preserving SRAM architecture for color motion pictures (WY, MC, SM), pp. 103–108.

DATE-2013-ZordanBDGTVB #fault #power management

Test solution for data retention faults in low-power SRAMs (LBZ, AB, LD, PG, AT, AV, NB), pp. 442–447.

HPCA-2013-ChangRLJ #comparison #energy #scalability

Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM (MTC, PR, SLL, BJ), pp. 143–154.

DAC-2012-DonkohLS #adaptation #design #hybrid #predict #using

A hybrid and adaptive model for predicting register file and SRAM power using a reference design (ED, AL, ES), pp. 62–67.

DATE-2012-HuangHLLLG #power management

Off-path leakage power aware routing for SRAM-based FPGAs (KH, YH, XL, BL, HL, JG), pp. 87–92.

DATE-2012-MakosiejTVA #design #embedded #optimisation #power management

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization (AM, OT, AV, AA), pp. 93–98.

DATE-2012-SchrijenL #analysis #comparative

Comparative analysis of SRAM memories used as PUF primitives (GJS, VvdL), pp. 1319–1324.

DATE-2012-Shahid #estimation #performance

Cross entropy minimization for efficient estimation of SRAM failure rate (MAS), pp. 230–235.

DATE-2012-SharmaCAHCD #power management #variability

Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM (VS, SC, MA, JH, FC, WD), pp. 1042–1047.

DATE-2012-VatajeluF #evaluation #parametricity #performance #reliability

Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation (EIV, JF), pp. 1343–1348.

DAC-2011-AadithyaVDR #impact analysis #named #predict #probability #random

MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs (KVA, SV, AD, JSR), pp. 292–297.

DAC-2011-DongL #performance #predict

Efficient SRAM failure rate prediction via Gibbs sampling (CD, XL), pp. 200–205.

DAC-2011-FajardoFIGLZ #architecture #effectiveness #embedded #named

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms (CFF, ZF, RI, GFG, SEL, LZ), pp. 966–971.

DATE-2011-AadithyaDVR #modelling #named #random #simulation

SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs (KVA, AD, SV, JSR), pp. 1113–1118.

DATE-2011-AlordaTBS #embedded #optimisation #using

Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation (BA, GT, SAB, JS), pp. 986–991.

DATE-2011-AsenovBC #aspect-oriented #statistics

Statistical aspects of NBTI/PBTI and impact on SRAM yield (AA, ARB, BC), pp. 1480–1485.

DATE-2011-ChandraA

Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown (VC, RCA), pp. 1172–1175.

DATE-2011-LiZY

Proactive recovery for BTI in high-k SRAM cells (LL, YZ, JY), pp. 992–997.

DATE-2011-MirandaZDR #logic #modelling #variability

Variability aware modeling for yield enhancement of SRAM and logic (MM, PZ, PD, PR), pp. 1153–1158.

DATE-2011-NalamCAC

Dynamic write limited minimum operating voltage for nanoscale SRAMs (SN, VC, RCA, BHC), pp. 467–472.

DATE-2011-SterponeCMWF #configuration management #power management

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.

DATE-2011-TsengHWFC #black box #compilation #library #modelling #power management

Black-box leakage power modeling for cell library and SRAM compiler (CKT, SYH, CCW, SCF, JJC), pp. 637–642.

DATE-2011-VatajeluF #analysis #in memory #memory management #robust

Robustness analysis of 6T SRAMs in memory retention mode under PVT variations (EIV, JF), pp. 980–985.

DATE-2011-YangM #design #robust

Robust 6T Si tunneling transistor SRAM design (XY, KM), pp. 740–745.

DAC-2010-CabeQS #power management

Stacking SRAM banks for ultra low power standby mode operation (ACC, ZQ, MRS), pp. 699–704.

DAC-2010-ChellappaNYHVCCC #variability

In-situ characterization and extraction of SRAM variability (SC, JN, XY, NDH, JV, MC, YC, LTC), pp. 711–716.

DAC-2010-FonsecaDBGPVB #analysis #reliability #simulation #statistics

A statistical simulation method for reliability analysis of SRAM core-cells (RAF, LD, AB, PG, SP, AV, NB), pp. 853–856.

DAC-2010-NalamBMC #design #optimisation #prototype

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers (SN, MB, KM, BHC), pp. 138–143.

DAC-2010-QiWCWBCS #design

SRAM-based NBTI/PBTI sensor system design (ZQ, JW, ACC, SNW, TNB, BHC, MRS), pp. 849–852.

DAC-2010-ZhangLH #analysis

Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis (YZ, PL, GMH), pp. 567–572.

DAC-2010-ZuberDM #analysis #approach #statistics

A holistic approach for statistical SRAM analysis (PZ, PD, MM), pp. 717–722.

DATE-2010-AlordaTBS #power management

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs (BA, GT, SAB, JS), pp. 429–434.

DATE-2010-ChandraPA #on the

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs (VC, CP, RCA), pp. 345–350.

DATE-2010-FacchiniMCD #3d #configuration management #memory management

An RDL-configurable 3D memory tier to replace on-chip SRAM (MF, PM, FC, WD), pp. 291–294.

DATE-2010-QaziTDSC #analysis #performance #reduction

Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis (MQ, MT, LD, DS, AC), pp. 801–806.

DATE-2010-SterponeB #algorithm #multi

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs (LS, NB), pp. 1231–1236.

DATE-2010-WieckowskiSBCIPA #analysis #black box

A black box method for stability analysis of arbitrary SRAM cell structures (MW, DS, DB, VC, SI, CP, RCA), pp. 795–800.

DATE-2010-ZuberMDZJ #analysis #statistics

Statistical SRAM analysis for yield enhancement (PZ, MM, PD, KvdZ, JHJ), pp. 57–62.

DAC-2009-ChangMR #architecture #hybrid #process #video

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors (IJC, DM, KR), pp. 670–675.

DAC-2009-WangYLP #analysis #parametricity

SRAM parametric failure analysis (JW, SY, XL, LTP), pp. 496–501.

DATE-2009-ChandraA #reliability #scalability

Impact of voltage scaling on nanoscale SRAM reliability (VC, RCA), pp. 387–392.

DATE-2009-NeyDGPVBG #fault

A new design-for-test technique for SRAM core-cell stability faults (AN, LD, PG, SP, AV, MB, VG), pp. 1344–1348.

DATE-2009-SasanHEK #process #scalability

Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling (AS, HH, AME, FJK), pp. 911–916.

DATE-2009-SinghPHMM #embedded #power management

Single ended 6T SRAM with isolated read-port for low-power embedded systems (JS, DKP, SH, SPM, JM), pp. 917–922.

DATE-2009-VignonCDMF #3d #architecture #novel

A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context (AV, SC, WD, PM, MF), pp. 929–933.

DAC-2008-Abu-RahmaCWCYA #estimation #statistics

A methodology for statistical estimation of read access yield in SRAMs (MHAR, KC, JW, ZC, SSY, MA), pp. 205–210.

DAC-2008-KulkarniKPR #array #process

Process variation tolerant SRAM array for ultra low voltage applications (JPK, KK, SPP, KR), pp. 108–113.

DAC-2008-MaestroR #reliability

Study of the effects of MBUs on the reliability of a 150 nm SRAM device (JAM, PR), pp. 930–935.

DATE-2008-NeyGPVBG

A Design-for-Diagnosis Technique for SRAM Write Drivers (AN, PG, SP, AV, MB, VG), pp. 1480–1485.

DATE-2008-SterponeATG #design #fault tolerance #on the #safety

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications (LS, MAA, JNT, HGM), pp. 336–341.

DATE-2007-AitkenI #design #embedded #worst-case

Worst-case design and margin for embedded SRAM (RCA, SI), pp. 1289–1294.

DATE-2007-GillPW #fault #interactive #power management #symmetry

Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA (BSG, CAP, FGW), pp. 1460–1465.

DATE-2007-NeyGLPVB #analysis #fault

Slow write driver faults in 65nm SRAM technology: analysis and March test solution (AN, PG, CL, SP, AV, MB), pp. 528–533.

DAC-2006-AgarwalN #analysis #statistics

Statistical analysis of SRAM cell stability (KA, SRN), pp. 57–62.

DAC-2006-GhoshMKR #power management #reduction #self

Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM (SG, SM, KK, KR), pp. 971–976.

DAC-2006-KanjJN #analysis #design

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events (RK, RVJ, SRN), pp. 69–72.

DATE-2006-AmelifardFP #using

Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment (BA, FF, MP), pp. 995–1000.

DATE-2006-BensoBCNP #automation #fault #testing

Automatic march tests generations for static linked faults in SRAMs (AB, AB, SDC, GDN, PP), pp. 1258–1263.

DATE-2006-ChenMBR #case study #design #power management

Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design (QC, SM, AB, KR), pp. 983–988.

DATE-2006-DililloRAG #process #reduction

Minimizing test power in SRAM through reduction of pre-charge activity (LD, PMR, BMAH, PG), pp. 1159–1164.

DAC-2005-DililloGPVB #analysis #comparison #fault #injection

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies (LD, PG, SP, AV, MB), pp. 857–862.

DATE-2005-KastensmidtSCR #composition #design #logic #on the

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs (FLK, LS, LC, MSR), pp. 1290–1295.

DATE-2005-WangMDCM #analysis #embedded #energy #process #variability

Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules (HW, MM, WD, FC, KM), pp. 914–919.

DATE-2005-WangWI #distributed #embedded #performance

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs (BW, YW, AI), pp. 852–857.

DATE-v1-2004-BellatoBBCCPRRVZ #memory management

Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA (MB, PB, DB, AC, MC, AP, MR, MSR, MV, PZ), pp. 584–589.

DAC-2003-JainSD #embedded

Embedded intelligent SRAM (PJ, GES, SD), pp. 869–874.

DAC-2003-LimaCR #design #fault tolerance

Designing fault tolerant systems into SRAM-based FPGAs (FL, LC, RAdLR), pp. 650–655.

DATE-2002-GericotaASF #concurrent #configuration management #novel

A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs (MGG, GRA, MLS, JMF), p. 1126.

DATE-2002-KumarMB #embedded #testing

IDDT Testing of Embedded CMOS SRAMs (SAK, RZM, DMB), p. 1117.

DATE-1999-RenovellPFZ #configuration management #interface #logic #testing

Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s (MR, JMP, JF, YZ), pp. 618–622.

HPCA-1998-MogaD #clustering #effectiveness #network

The Effectiveness of SRAM Network Caches in Clustered DSMs (AM, MD), pp. 103–112.

EDTC-1997-AbdullaRK #embedded #multi

A scheme for multiple on-chip signature checking for embedded SRAMs (MFA, CPR, AK), p. 625.

EDAC-1994-AGZS #functional #testing

Functional Tests for Ring-Address SRAM-type FIFOs (AJvdG, YZ, IS), p. 666.