A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR
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Thomas Froehlich, Vivek Sharma, Markus Bingesser
A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR
DATE, 2010.

DATE 2010
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@inproceedings{DATE-2010-FroehlichSB,
	author        = "Thomas Froehlich and Vivek Sharma and Markus Bingesser",
	booktitle     = "{Proceedings of the 14th Conference on Design, Automation and Test in Europe}",
	pages         = "706--710",
	publisher     = "{IEEE}",
	title         = "{A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR}",
	year          = 2010,
}


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