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Used together with:
design (10)
pipelin (8)
bit (6)
base (5)
power (5)

Stem adc$ (all stems)

30 papers:

DATEDATE-2015-BrennaBBL #design
A tool for the assisted design of charge redistribution SAR ADCs (SB, AB, AB, ALL), pp. 1265–1268.
DATEDATE-2015-ErolOSPB #metric #using
On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC (OEE, SO, CKHS, RAP, LB), pp. 1559–1562.
AdaEuropeAdaEurope-2015-ZamoranoG #analysis #scheduling
Schedulability Analysis of PWM Tasks for the UPMSat-2 ADCS (JZ, JG), pp. 85–99.
DACDAC-2014-LiuCHWXY #3d #design
Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case (WL, GC, XH, YW, YX, HY), p. 6.
DATEDATE-2014-LeeA #architecture #hybrid #novel #power management #using
A novel low power 11-bit hybrid ADC using flash and delay line architectures (HCL, JAA), pp. 1–4.
DACDAC-2013-YeWHL #parallel #segmentation #simulation
Time-domain segmentation based massively parallel simulation for ADCs (ZY, BW, SH, YL), p. 6.
DATEDATE-2012-GaoXCG #design
Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping (PG, XX, JC, GGEG), pp. 1215–1220.
DACDAC-2011-ChangC #3d #array #image #metric #performance #quality #specification
Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers (HMC, KT(C), pp. 759–764.
DATEDATE-2010-FroehlichSB
A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR (TF, VS, MB), pp. 706–710.
DATEDATE-2010-HuangCLH #robust
A robust ADC code hit counting technique (JLH, KYC, MHL, XLH), pp. 1749–1754.
DATEDATE-2010-VenutoSCP #power management
Ultra low-power 12-bit SAR ADC for RFID applications (DDV, ES, DTC, YP), pp. 1071–1075.
DATEDATE-2009-Diaz-MadridNHDR #pipes and filters #reduction
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing (JÁDM, HN, HH, GDA, RRM), pp. 369–373.
DATEDATE-2008-LiCZ #novel
A Novel Technique for Improving Temperature Independency of Ring-ADC (SL, HC, FZ), pp. 694–697.
DATEDATE-2008-VenutoR #generative
PWM-Based Test Stimuli Generation for BIST of High Resolution ADCs (DDV, LR), pp. 284–287.
DATEDATE-2007-AminzadehDL #design #pipes and filters
Design of high-resolution MOSFET-only pipelined ADCs with digital calibration (HA, MD, RL), pp. 427–432.
DATEDATE-2007-ErdoganO #analysis #using
An ADC-BiST scheme using sequential code analysis (ESE, SO), pp. 713–718.
DACDAC-2006-NuzzoPBPGT
A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW (PN, GVdP, FDB, LVdP, BG, PT), pp. 873–878.
DACDAC-2006-YuL #modelling #simulation #statistics
Lookup table based simulation and statistical modeling of Sigma-Delta ADCs (GY, PL), pp. 1035–1040.
DATEDATE-2006-MajidzadehS #design #higher-order #novel
Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs (VM, OS), pp. 138–143.
DATEDATE-2005-BarrandonCH #design #pipes and filters
Systematic Figure of Merit Computation for the Design of Pipeline ADC (LB, SC, DH), pp. 277–278.
DATEDATE-v1-2004-GinesPR #fault #pipes and filters
Digital Background Gain Error Correction in Pipeline ADCs (AJG, EJP, AR), pp. 82–87.
DATEDATE-v1-2004-Taherzadeh-SaniLS #design #optimisation #pipes and filters
Systematic Design for Optimization of High-Resolution Pipelined ADCs (MTS, RL, OS), pp. 678–679.
DATEDATE-2005-AndersenBTBBHM04 #pipes and filters
A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS (TNA, AB, FT, JB, TEB, BH, ØM), pp. 219–222.
DATEDATE-2005-SandnerCSHK04 #power management
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS (CS, MC, AS, TH, FK), pp. 223–226.
DACDAC-2002-BajdechiHG #design
Optimal design of delta-sigma ADCs by design space exploration (OB, JHH, GGEG), pp. 443–448.
DACDAC-2001-GorenSW #analysis #novel #pipes and filters #probability
A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC (DG, ES, IAW), pp. 127–132.
DATEDATE-2001-AzaisBBR #implementation #linear
Implementation of a linear histogram BIST for ADCs (FA, SB, YB, MR), pp. 590–595.
DATEDATE-2001-LechnerRH #comprehension #requirements #towards
Towards a better understanding of failure modes and test requirements of ADCs (AL, AR, BH), p. 803.
DATEDATE-2000-HuangOC #testing
A BIST Scheme for On-Chip ADC and DAC Testing (JLH, CKO, KTC), pp. 216–220.
DATEDATE-2000-WenL
An on Chip ADC Test Structure (YCW, KJL), pp. 221–225.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.