BibSLEIGH — Proceedings of the 14th Conference on Design, Automation and Test in Europe

Proceedings of the 14th Conference on Design, Automation and Test in Europe
DATE, 2010.

SYS

@proceedings{DATE-2010,
	address       = "Dresden, Germany",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 14th Conference on Design, Automation and Test in Europe}",
	year          = 2010,
}

Contents (344 items)

DATE-2010-Sangiovanni-Vincentelli: All things are connected (ALSV), p. 1.
DATE-2010-Eul #communication #difference #standard: Wireless communication — successful differentiation on standard technology by innovation (HE), p. 2.
DATE-2010-Benveniste #architecture #cyber-physical: Loosely Time-Triggered Architectures for Cyber-Physical Systems (AB), pp. 3–8.
DATE-2010-YangCTK #energy #realtime #scheduling: Energy-efficient real-time task scheduling with temperature-dependent leakage (CYY, JJC, LT, TWK), pp. 9–14.
DATE-2010-PenolazziSH #energy #operating system #performance #predict #realtime: Predicting energy and performance overhead of Real-Time Operating Systems (SP, IS, AH), pp. 15–20.
DATE-2010-BaoAEP #energy #optimisation #scalability: Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling (MB, AA, PE, ZP), pp. 21–26.
DATE-2010-VadlamaniZBT #adaptation #composition #fault #manycore #using: Multicore soft error rate stabilization using adaptive dual modular redundancy (RV, JZ, WPB, RT), pp. 27–32.
DATE-2010-ThonnartVC #framework #integration #power management: A fully-asynchronous low-power framework for GALS NoC integration (YT, PV, FC), pp. 33–38.
DATE-2010-ChenLJC #distributed #manycore #memory management #using: Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller (XC, ZL, AJ, SC), pp. 39–44.
DATE-2010-TotaCRRZ #architecture #hybrid #message passing #multi #named: MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture (ST, MRC, MRR, LR, MZ), pp. 45–50.
DATE-2010-HuangX #framework #named #reliability #simulation: AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs (LH, QX), pp. 51–56.
DATE-2010-ZuberMDZJ #analysis #statistics: Statistical SRAM analysis for yield enhancement (PZ, MM, PD, KvdZ, JHJ), pp. 57–62.
DATE-2010-ChenO #adaptation #effectiveness #identification: Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme (MC, AO), pp. 63–68.
DATE-2010-YangAFK #design #power management #reliability: Scan based methodology for reliable state retention power gating designs (SY, BMAH, DF, SSK), pp. 69–74.
DATE-2010-EckerESSV #embedded #modelling: TLM+ modeling of embedded HW/SW systems (WE, VE, RS, TS, MV), pp. 75–80.
DATE-2010-TraubSKB #network: Scenario extraction for a refined timing-analysis of automotive network topologies (MT, TS, OK, JB), pp. 81–86.
DATE-2010-ZengGA #debugging #embedded #framework #visual notation: Graphical Model Debugger Framework for embedded systems (KZ, YG, CA), pp. 87–92.
DATE-2010-MuZZLDZ: IP routing processing with graphic processors (SM, XZ, NZ, JL, YSD, SZ), pp. 93–98.
DATE-2010-LoiB #3d #distributed #framework #interface #manycore #memory management #performance: An efficient distributed memory interface for many-core platform with 3D stacked DRAM (IL, LB), pp. 99–104.
DATE-2010-MarongiuRB #manycore #memory management #performance: Efficient OpenMP data mapping for multicore platforms with vertically stacked memory (AM, MR, LB), pp. 105–110.
DATE-2010-CoskunARBM #3d #architecture #energy: Energy-efficient variable-flow liquid cooling in 3D stacked architectures (AKC, DA, TSR, TB, BM), pp. 111–116.
DATE-2010-LongMG #optimisation: Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers (JL, SOM, MG), pp. 117–122.
DATE-2010-MoyerKCRHT #assembly #question: Are we there yet? Has IP block assembly become as easy as LEGO? (BM, JK, JC, CR, EH, YT), p. 123.
DATE-2010-PakbazniaGP #power management #resource management: Temperature-aware dynamic resource provisioning in a power-optimized datacenter (EP, MG, MP), pp. 124–129.
DATE-2010-HenryN #power management: From transistors to MEMS: Throughput-aware power gating in CMOS circuits (MBH, LN), pp. 130–135.
DATE-2010-JooNDSCX #design #energy #memory management: Energy- and endurance-aware design of phase change memory caches (YJ, DN, XD, GS, NC, YX), pp. 136–141.
DATE-2010-AliARA #algorithm #design #energy #evaluation #predict: Evaluation and design exploration of solar harvested-energy prediction algorithm (MIA, BMAH, JR, DA), pp. 142–147.
DATE-2010-ChenLWZXZ #memory management #random #self: A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) (YC, HL, XW, WZ, WX, TZ), pp. 148–153.
DATE-2010-HuangFLYSSC #design #flexibility #named #novel #pseudo: Pseudo-CMOS: A novel design style for flexible electronics (TCH, KF, CML, YHY, TS, TS, KTC), pp. 154–159.
DATE-2010-GarciaM #energy #named: Spinto: High-performance energy minimization in spin glasses (HJG, ILM), pp. 160–165.
DATE-2010-HsiehHCTTL #3d #architecture #design: TSV redundancy: Architecture and design issues in 3D IC (ACH, TH, MTC, MHT, CMT, HCL), pp. 166–171.
DATE-2010-RathiDGCV #distance #feature model #gpu #implementation: A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching (AR, MD, WG, RTC, NV), pp. 172–177.
DATE-2010-GrottesiMRB #animation #parallel: Parallel subdivision surface rendering and animation on the Cell BE processor (RG, SM, MR, LB), pp. 178–183.
DATE-2010-JalierLJSBT #mobile: Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem (CJ, DL, AAJ, GS, PB, LT), pp. 184–189.
DATE-2010-CollinsVC #code generation #manycore #parallel #recursion: Recursion-driven parallel code generation for multi-core platforms (RLC, BV, LPC), pp. 190–195.
DATE-2010-MarianiAVYPSZ #design #framework #industrial #manycore #resource management #runtime: An industrial design space exploration framework for supporting run-time resource management on multi-core systems (GM, PA, GV, CYC, GP, CS, VZ), pp. 196–201.
DATE-2010-MajidK #performance: Stretching the limits of FPGA SerDes for enhanced ATE performance (AMM, DCK), pp. 202–207.
DATE-2010-HePE #multi #testing: Multi-temperature testing for core-based system-on-chip (ZH, ZP, PE), pp. 208–213.
DATE-2010-GoorGH #memory management #testing: Memory testing with a RISC microcontroller (AJvdG, GG, SH), pp. 214–219.
DATE-2010-MasrurCF: Constant-time admission control for Deadline Monotonic tasks (AM, SC, GF), pp. 220–225.
DATE-2010-RoxE #correlation: Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks (JR, RE), pp. 226–231.
DATE-2010-KootiBLB #configuration management #embedded #realtime #scheduling: Transition-aware real-time task scheduling for reconfigurable embedded systems (HK, EB, SL, LB), pp. 232–237.
DATE-2010-PanHL #fault #named: IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults (SP, YH, XL), pp. 238–243.
DATE-2010-DadgourB #architecture #design #detection #novel #pipes and filters #using: Aging-resilient design of pipelined architectures using novel detection and correction circuits (HFD, KB), pp. 244–249.
DATE-2010-AziziMSPH #architecture #design #framework: An integrated framework for joint design space exploration of microarchitecture and circuits (OA, AM, JPS, SJP, MH), pp. 250–255.
DATE-2010-Furst #challenge #design: Challenges in the design of automotive software (SF), pp. 256–258.
DATE-2010-Voget: AUTOSAR and the automotive tool chain (SV), pp. 259–262.
DATE-2010-Diekhoff: AUTOSAR basic software for complex control units (DD), pp. 263–266.
DATE-2010-CaoN #markov #protocol: High-fidelity markovian power model for protocols (JC, AN), pp. 267–270.
DATE-2010-GellertPZFVS #architecture #design #energy #predict #smt: Energy-performance design space exploration in SMT architectures exploiting selective load value predictions (AG, GP, VZ, AF, LNV, CS), pp. 271–274.
DATE-2010-PascaARLC #3d #communication #fault: Error resilience of intra-die and inter-die communication with 3D spidergon STNoC (VP, LA, CR, RL, MC), pp. 275–278.
DATE-2010-BashirM #process #reliability #towards: Towards a chip level reliability simulator for copper/low-k backend processes (MB, LSM), pp. 279–282.
DATE-2010-SeyabH #framework #modelling: NBTI modeling in the framework of temperature variation (S, SH), pp. 283–286.
DATE-2010-WenCCL #debugging #named #parallel #runtime #source code: RunAssert: A non-intrusive run-time assertion for parallel programs debugging (CNW, SHC, TFC, TJL), pp. 287–290.
DATE-2010-FacchiniMCD #3d #configuration management #memory management: An RDL-configurable 3D memory tier to replace on-chip SRAM (MF, PM, FC, WD), pp. 291–294.
DATE-2010-AyoubSR #multi #named #scheduling: GentleCool: Cooling aware proactive workload scheduling in multi-machine systems (RZA, SS, TSR), pp. 295–298.
DATE-2010-LotzeGM #modelling: Timing modeling for digital sub-threshold circuits (NL, JG, YM), pp. 299–302.
DATE-2010-JamaaMM #logic #power management: Power consumption of logic circuits in ambipolar carbon nanotube technology (MHBJ, KM, GDM), pp. 303–306.
DATE-2010-LiZHH #logic #optimisation #synthesis: Reversible logic synthesis through ant colony optimization (ML, YZ, MSH, CH), pp. 307–310.
DATE-2010-MishraJ #optimisation #power management #synthesis #using: Low-power FinFET circuit synthesis using surface orientation optimization (PM, NKJ), pp. 311–314.
DATE-2010-BollapalliKK #implementation #logic: Implementing digital logic with sinusoidal supplies (KCB, SPK, LBK), pp. 315–318.
DATE-2010-TumeoRPFS #architecture #configuration management #implementation #multi #recognition #reliability: A reconfigurable multiprocessor architecture for a reliable face recognition implementation (AT, FR, GP, FF, DS), pp. 319–322.
DATE-2010-Krupp0 #approach: A systematic approach to the test of combined HW/SW systems (AK, WM), pp. 323–326.
DATE-2010-OstendorffWSK #adaptation #approach: A new approach for adaptive failure diagnostics based on emulation test (SO, HDW, JS, SK), pp. 327–330.
DATE-2010-LakshmananBR #analysis: Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems (KL, GB, RR), pp. 331–334.
DATE-2010-NarayananSKJ #probability #scalability: Scalable stochastic processors (SN, JS, RK, DLJ), pp. 335–338.
DATE-2010-Kheradmand-BoroujeniPL #independence #novel #process: AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics (BKB, CP, YL), pp. 339–344.
DATE-2010-ChandraPA #on the: On the efficacy of write-assist techniques in low voltage nanoscale SRAMs (VC, CP, RCA), pp. 345–350.
DATE-2010-JungP #network #nondeterminism #optimisation #power management: Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times (HJ, MP), pp. 351–356.
DATE-2010-BraakHKHS #realtime #resource management #runtime: Run-time spatial resource management for real-time applications on heterogeneous MPSoCs (TDtB, PKFH, JK, JH, GJMS), pp. 357–362.
DATE-2010-JavaidJHP #agile #estimation #pipes and filters #runtime: Rapid runtime estimation methods for pipelined MPSoCs (HJ, AJ, MSH, SP), pp. 363–368.
DATE-2010-KrekuTV #automation #compilation #generative: Automatic workload generation for system-level exploration based on modified GCC compiler (JK, KT, GV), pp. 369–374.
DATE-2010-MayWBZSHZT #agile #multi #prototype: A rapid prototyping system for error-resilient multi-processor systems-on-chip (MM, NW, AB, JZ, WS, AH, DZ, JT), pp. 375–380.
DATE-2010-ShenHH #adaptation #configuration management: Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip (JSS, CHH, PAH), pp. 381–386.
DATE-2010-WhittySHEP #architecture #configuration management #memory management #performance: Application-specific memory performance of a heterogeneous reconfigurable architecture (SW, HS, BH, RE, WPR), pp. 387–392.
DATE-2010-AkinSH #configuration management #estimation #hardware #multi: A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation (AA, GS, IH), pp. 393–398.
DATE-2010-KennedyWLL #string #throughput: Ultra-high throughput string matching for Deep Packet Inspection (AK, XW, ZL, BL), pp. 399–404.
DATE-2010-GiraldoMJM #hardware #using: A HMMER hardware accelerator using divergences (JFEG, NM, RPJ, ACMAdM), pp. 405–410.
DATE-2010-LiZYZ #functional: Proactive NBTI mitigation for busy functional units in out-of-order microprocessors (LL, YZ, JY, JZ), pp. 411–416.
DATE-2010-GanapathyCGR #estimation #modelling #multi #variability: Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability (SG, RC, AG, AR), pp. 417–422.
DATE-2010-ChoudhuryCMA #logic #performance: Analytical model for TDDB-based performance degradation in combinational logic (MRC, VC, KM, RCA), pp. 423–428.
DATE-2010-AlordaTBS #power management: Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs (BA, GT, SAB, JS), pp. 429–434.
DATE-2010-MichailidisSRHK #development: Test front loading in early stages of automotive software development based on AUTOSAR (AM, US, TR, BH, SK), pp. 435–440.
DATE-2010-BhaduriS #interface #realtime: A proposal for real-time interfaces in SPEEDS (PB, IS), pp. 441–446.
DATE-2010-LarsenLNP #analysis #realtime #synthesis #using: Scenario-based analysis and synthesis of real-time systems using uppaal (KGL, SL, BN, SP), pp. 447–452.
DATE-2010-El-MoselhyD #order #reduction #statistics #using: Variation-aware interconnect extraction using statistical moment preserving model order reduction (TAEM, LD), pp. 453–458.
DATE-2010-SrivastavaSB #3d #performance: Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate (NS, RS, KB), pp. 459–464.
DATE-2010-VillenaS #named #order #reduction: HORUS — high-dimensional Model Order Reduction via low moment-matching upgraded sampling (JFV, LMS), pp. 465–470.
DATE-2010-UgryumovaS #algorithm #modelling #on the: On passivity of the super node algorithm for EM modeling of interconnect systems (MVU, WHAS), pp. 471–476.
DATE-2010-Fettweis #energy: The road to energy-efficient systems: From hardware-driven to software-defined (GF), p. 477.
DATE-2010-GuglielmoFP #analysis: Vacuity analysis for property qualification by mutation of checkers (LDG, FF, GP), pp. 478–483.
DATE-2010-ZhangLL #approach #markov #modelling #simulation #using #verification: An abstraction-guided simulation approach using Markov models for microprocessor verification (TZ, TL, XL), pp. 484–489.
DATE-2010-ChenQM #generative #performance #satisfiability #testing: Efficient decision ordering techniques for SAT-based test generation (MC, XQ, PM), pp. 490–495.
DATE-2010-HaquePJP #approach #embedded #named #performance #policy #simulation: DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy (MSH, JP, AJ, SP), pp. 496–501.
DATE-2010-MohanGS #memory management #named: FlashPower: A detailed power model for NAND flash memory (VM, SG, MRS), pp. 502–507.
DATE-2010-GaoH #geometry #optimisation #programming #using: A power optimization method for CMOS Op-Amps using sub-space based geometric programming (WG, RH), pp. 508–513.
DATE-2010-ChenLTL #design #power management #standard: Power gating design for standard-cell-like structured ASICs (SYC, RBL, HHT, KWL), pp. 514–519.
DATE-2010-TieDWC #performance #reduction #scheduling: Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement (MT, HD, TW, XC), pp. 520–525.
DATE-2010-FanucciPDSTCLT #programmable: An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability (LF, GP, PD, RS, FT, PC, LL, PT), pp. 526–531.
DATE-2010-MullerBGRNZB #design #implementation #manycore #recognition: Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation (MM, AGB, JG, WR, DN, JMZ, OB), pp. 532–537.
DATE-2010-BraunBLR #interface #specification #verification: Simulation-based verification of the MOST NetInterface specification revision 3.0 (AB, OB, DL, WR), pp. 538–543.
DATE-2010-KarnerASW #network #runtime #simulation #using: Holistic simulation of FlexRay networks by using run-time model switching (MK, EA, CS, RW), pp. 544–549.
DATE-2010-GhosalZNB #design #nondeterminism #parametricity #robust: Computing robustness of FlexRay schedules to uncertainties in design parameters (AG, HZ, MDN, YBH), pp. 550–555.
DATE-2010-MarinissenSGECNBAP #adaptation #testing: Adapting to adaptive testing (EJM, AS, DG, ME, JMCJ, AN, KMB, DA, CP), pp. 556–561.
DATE-2010-ArtiagaC #metadata #using: Using filesystem virtualization to avoid metadata bottlenecks (EA, TC), pp. 562–567.
DATE-2010-HsuYC #architecture #framework #refinement: An accurate system architecture refinement methodology with mixed abstraction-level virtual platform (ZMH, JCY, IYC), pp. 568–573.
DATE-2010-BolteSBNB #using: Non-intrusive virtualization management using libvirt (MB, MS, GB, ON, AB), pp. 574–579.
DATE-2010-ZhuoSB #process #reliability: Process variation and temperature-aware reliability management (CZ, DS, DB), pp. 580–585.
DATE-2010-MintarnoSZVCBDM #self: Optimized self-tuning for circuit aging (EM, JS, RZ, JV, YC, SPB, RWD, SM), pp. 586–591.
DATE-2010-RickettsSRVP #power management: Investigating the impact of NBTI on different power saving cache strategies (AJR, JS, KR, NV, DKP), pp. 592–597.
DATE-2010-HuanYCM #energy #graph: Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph (WH, ZY, MC, LM), pp. 598–601.
DATE-2010-LiuTQ #algorithm #constraints #performance #power management: Enhanced Q-learning algorithm for dynamic power management with performance constraint (WL, YT, QQ), pp. 602–605.
DATE-2010-MelloMGP #parallel #simulation: Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations (AM, IM, AG, FP), pp. 606–609.
DATE-2010-HallerB #low cost #performance: High-speed clock recovery for low-cost FPGAs (IH, ZFB), pp. 610–613.
DATE-2010-ProssGMJLHKS #configuration management #network: Demonstration of an in-band reconfiguration data distribution and network node reconfiguration (UP, SG, EM, MJ, JL, UH, JK, AS), pp. 614–617.
DATE-2010-VazquezCTST #programmable #safety: Programmable aging sensor for automotive safety-critical applications (JCV, VHC, ICT, MBS, JPT), pp. 618–621.
DATE-2010-MahmoodBMMD #modelling #multi #order #programming: Passive reduced order modeling of multiport interconnects via semidefinite programming (ZM, BNB, TM, AM, LD), pp. 622–625.
DATE-2010-VasudevanSPTTJ #automation #data mining #generative #mining #named #static analysis #using: GoldMine: Automatic assertion generation using data mining and static analysis (SV, DS, SJP, DT, WT, DRJ), pp. 626–629.
DATE-2010-OliveiraZ0 #verification: Assertion-based verification of RTOS properties (MFdSO, HZ, WM), pp. 630–633.
DATE-2010-LiuNCMP #reduction: Post-placement temperature reduction techniques (WL, AN, AC, EM, MP), pp. 634–637.
DATE-2010-SrinivasJ #clustering #graph #performance: Clock gating approaches by IOEX graphs and cluster efficiency plots (JS, SJ), pp. 638–641.
DATE-2010-KlobedanzKT0 #analysis #case study #development #modelling: Timing modeling and analysis for AUTOSAR-based software development — a case study (KK, CK, AT, WM), pp. 642–645.
DATE-2010-KerstanO #design #realtime: Design of a real-time optimized emulation method (TK, MO), pp. 646–649.
DATE-2010-ChengDMMRWRA #parametricity #using: Capturing intrinsic parameter fluctuations using the PSP compact model (BC, DD, NM, CM, GR, XW, SR, AA), pp. 650–653.
DATE-2010-GhoshS #performance #perspective: Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective (PG, AS), pp. 654–657.
DATE-2010-Rabaey #energy: Always energy-optimal microscopic wireless systems (JMR), p. 658.
DATE-2010-AhlendorfG #challenge #design #hardware #monitoring #power management: Hardware / software design challenges of low-power sensor nodes for condition monitoring (HA, LG), p. 659.
DATE-2010-Barker #aspect-oriented #network #security: Security aspects in 6lowPan networks (RB), p. 660.
DATE-2010-StrukovM #hybrid: Monolithically stackable hybrid FPGA (DBS, AM), pp. 661–666.
DATE-2010-WangC: Spintronic memristor devices and application (XW, YC), pp. 667–672.
DATE-2010-LiH: Compact model of memristors and its application in computing systems (HL, MH), pp. 673–678.
DATE-2010-LudoviciSGBB #design #effectiveness #flexibility: Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs (DL, AS, GNG, LB, DB), pp. 679–684.
DATE-2010-HernandezSD #process: A methodology for the characterization of process variation in NoC links (CH, FS, JD), pp. 685–690.
DATE-2010-ChanHBBC #analysis #named #network: PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks (JC, GH, AB, KB, LPC), pp. 691–696.
DATE-2010-GeisNRRVC: An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation (AG, PN, JR, YR, GV, JC), pp. 697–701.
DATE-2010-ChironiDBCI: A compact digital amplitude modulator in 90nm CMOS (VC, BD, AB, JC, MI), pp. 702–705.
DATE-2010-FroehlichSB: A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR (TF, VS, MB), pp. 706–710.
DATE-2010-TajalliL #design #framework #power management #using: Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits (AT, YL), pp. 711–716.
DATE-2010-WuM #scheduling: Clock skew scheduling for soft-error-tolerant sequential circuits (KCW, DM), pp. 717–722.
DATE-2010-Scholzel #detection #fault #performance: HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data paths (MS), pp. 723–728.
DATE-2010-KarmarkarT #generative #scalability: Scalable codeword generation for coupled buses (KK, ST), pp. 729–734.
DATE-2010-ChenW #adaptation #memory management #random: An adaptive code rate EDAC scheme for random access memory (CYC, CWW), pp. 735–740.
DATE-2010-PellizzoniSCCT #analysis #manycore #memory management: Worst case delay analysis for memory interference in multicore systems (RP, AS, JJC, MC, LT), pp. 741–746.
DATE-2010-MeijerNS #modelling #network #process #throughput: Throughput modeling to evaluate process merging transformations in polyhedral process networks (SM, HN, TS), pp. 747–752.
DATE-2010-CastrillonVSSCLAM #analysis: Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms (JC, RV, AS, WS, JC, RL, GA, HM), pp. 753–758.
DATE-2010-SchlieckerNE #analysis #bound #multi #performance: Bounding the shared resource load for the performance analysis of multiprocessor systems (SS, MN, RE), pp. 759–764.
DATE-2010-AgyekumN #communication #hardware #robust: An error-correcting unordered code and hardware support for robust asynchronous global communication (MYA, SMN), pp. 765–770.
DATE-2010-KatebiM #scalability: Large-scale Boolean matching (HK, ILM), pp. 771–776.
DATE-2010-MartinelloMRR #approach #logic #multi #named #synthesis: KL-Cuts: A new approach for logic synthesis targeting multiple output blocks (OM, FSM, RPR, AIR), pp. 777–782.
DATE-2010-LuckenbillLHMH #algorithm #analysis #fault #logic #named #reliability: RALF: Reliability Analysis for Logic Faults — An exact algorithm and its applications (SBL, JYL, YH, RM, LH), pp. 783–788.
DATE-2010-Horowitz #design #why: Why design must change: Rethinking digital design (MH), p. 791.
DATE-2010-RaabBHLSESE #design #power management: Low power design of the X-GOLD® SDR 20 baseband processor (WR, JB, JAUH, DL, MS, HE, JUS, GE), pp. 792–793.
DATE-2010-Aue #internet #mobile #power management #using: Low power mobile internet devices using LTE technology (VA), p. 794.
DATE-2010-WieckowskiSBCIPA #analysis #black box: A black box method for stability analysis of arbitrary SRAM cell structures (MW, DS, DB, VC, SI, CP, RCA), pp. 795–800.
DATE-2010-QaziTDSC #analysis #performance #reduction: Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis (MQ, MT, LD, DS, AC), pp. 801–806.
DATE-2010-JaffariA #estimation #monte carlo: Practical Monte-Carlo based timing yield estimation of digital circuits (JJ, MA), pp. 807–812.
DATE-2010-KanoriaMM #analysis #markov #monte carlo #statistics #using: Statistical static timing analysis using Markov chain Monte Carlo (YK, SM, AM), pp. 813–818.
DATE-2010-KoenigBSSABH #architecture #configuration management #multi #named #novel: KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture (RK, LB, TS, MS, WA, JB, JH), pp. 819–824.
DATE-2010-BenitezMRL #configuration management #memory management: A reconfigurable cache memory with heterogeneous banks (DB, JCM, DR, EL), pp. 825–830.
DATE-2010-SigdelTGPB #case study #evaluation #heuristic #runtime: Evaluation of runtime task mapping heuristics with rSesame — a case study (KS, MT, CG, ADP, KB), pp. 831–836.
DATE-2010-Jara-BerrocalG #architecture #configuration management #embedded #named: VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems (AJB, AGR), pp. 837–842.
DATE-2010-ChenS #implementation #manycore #named #parallel #scalability: pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems (ZC, PS), pp. 843–848.
DATE-2010-NassarBDDG #evaluation #named: BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation (MN, SB, JLD, GD, SG), pp. 849–854.
DATE-2010-PellegriniBA #authentication: Fault-based attack of RSA authentication (AP, VB, TMA), pp. 855–860.
DATE-2010-DasMZC #detection #hardware #information management #memory management: Detecting/preventing information leakage on the memory bus due to malicious hardware (AD, GM, JZ, ANC), pp. 861–866.
DATE-2010-BalaschVP #embedded #framework #privacy: An embedded platform for privacy-friendly road charging applications (JB, IV, BP), pp. 867–872.
DATE-2010-BalatsoukaTKC #fault #power management #testing: Defect aware X-filling for low-power scan testing (SB, VT, XK, KC), pp. 873–878.
DATE-2010-UbarDRJ #parallel #simulation: Parallel X-fault simulation with critical path tracing technique (RU, SD, JR, AJ), pp. 879–884.
DATE-2010-YeHL #fault #multi: Diagnosis of multiple arbitrary faults with mask and reinforcement effect (JY, YH, XL), pp. 885–890.
DATE-2010-CanedoYK #parallel #pipes and filters #simulation: Skewed pipelining for parallel simulink simulations (AC, TY, HK), pp. 891–896.
DATE-2010-BonfiettiBLM #approach #manycore #performance #scheduling: An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms (AB, LB, ML, MM), pp. 897–902.
DATE-2010-NeukirchnerSSE #self: A software update service with self-protection capabilities (MN, SS, HS, RE), pp. 903–908.
DATE-2010-KlemmF #c++ #embedded #metaprogramming #using: Bitstream processing for embedded systems using C++ metaprogramming (RK, GF), pp. 909–913.
DATE-2010-FerreiraZBCMM #in memory #memory management: Increasing PCM main memory lifetime (APF, MZ, SB, BRC, RGM, DM), pp. 914–919.
DATE-2010-JanapsatyaIPP #adaptation #algorithm #policy: Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm (AJ, AI, JP, SP), pp. 920–925.
DATE-2010-Yu: A memory- and time-efficient on-chip TCAM minimizer for IP lookup (HY), pp. 926–931.
DATE-2010-FuHLL: Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs (BF, YH, HL, XL), pp. 933–936.
DATE-2010-PasettiFS #power management: A High-Voltage Low-Power DC-DC buck regulator for automotive applications (GP, LF, RS), pp. 937–940.
DATE-2010-KimKL #named #reliability #similarity: SimTag: Exploiting tag bits similarity to improve the reliability of the data caches (JK, SK, YL), pp. 941–944.
DATE-2010-AbellaCCV: The split register file (JA, JC, PC, XV), pp. 945–948.
DATE-2010-BaudischBS #independence #parallel #source code #thread: Multithreaded code from synchronous programs: Extracting independent threads for OpenMP (DB, JB, KS), pp. 949–952.
DATE-2010-IqbalSH #estimation #execution #named #order #pipes and filters #recursion: RMOT: Recursion in model order for task execution time estimation in a software pipeline (NI, MAS, JH), pp. 953–956.
DATE-2010-ShinG #approximate #fault #logic #synthesis: Approximate logic synthesis for error tolerant applications (DS, SKG), pp. 957–960.
DATE-2010-OmsCBK #architecture #automation #pipes and filters: Automatic microarchitectural pipelining (MGO, JC, DB, MK), pp. 961–964.
DATE-2010-RitheGWDGBC #analysis #logic #statistics: Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage (RR, JG, AW, SD, GG, DB, AC), pp. 965–968.
DATE-2010-WongAN #configuration management: Dynamically reconfigurable register file for a softcore VLIW processor (SW, FA, FN), pp. 969–972.
DATE-2010-LiuLKJ #adaptation #correlation #multi: FPGA-based adaptive computing for correlated multi-stream processing (ML, ZL, WK, AJ), pp. 973–976.
DATE-2010-MeynardGDS: Far Correlation-based EMA with a precharacterized leakage model (OM, SG, JLD, LS), pp. 977–980.
DATE-2010-IzumiISO #multi: Improved countermeasure against Address-bit DPA for ECC scalar multiplication (MI, JI, KS, KO), pp. 981–984.
DATE-2010-NeishaburiZ #clustering #debugging #performance: Enabling efficient post-silicon debug by clustering of hardware-assertions (MHN, ZZ), pp. 985–988.
DATE-2010-BellasiBCFS #framework #mobile #multi #power management: Constrained Power Management: Application to a multimedia mobile platform (PB, SB, MC, WF, DS), pp. 989–992.
DATE-2010-MehdipourHKIKMAF #quantum #scalability: Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits (FM, HH, HK, KI, IK, KM, HA, AF), pp. 993–996.
DATE-2010-KranenburgL #architecture #implementation #named #robust: MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture (TK, RvL), pp. 997–1000.
DATE-2010-NurvitadhiHKL #automation #pipes and filters #specification #transaction: Automatic pipelining from transactional datapath specifications (EN, JCH, TK, SLL), pp. 1001–1004.
DATE-2010-Schlager #hardware #interactive #performance: Increasing the power efficiency of PCs by improving the hardware/OS interaction (CS), p. 1005.
DATE-2010-Flautner #performance: Optimize your power and performance yields and regain those sleepless nights (KF), p. 1006.
DATE-2010-DietrichEH #analysis #statistics #using: Digital statistical analysis using VHDL (MD, UE, JH), pp. 1007–1010.
DATE-2010-NassifMC #roadmap: A resilience roadmap (SRN, NM, YC), pp. 1011–1016.
DATE-2010-DeHonQC #challenge #energy #optimisation #reliability: Vision for cross-layer optimization to address the dual challenges of energy and reliability (AD, HMQ, NPC), pp. 1017–1022.
DATE-2010-CarterNG #design: Design techniques for cross-layer resilience (NPC, HN, DSG), pp. 1023–1028.
DATE-2010-MitraBS #challenge #metric #optimisation: Cross-layer resilience challenges: Metrics and optimization (SM, KB, PNS), pp. 1029–1034.
DATE-2010-ZhuSJ #configuration management #cpu #design #performance #streaming: Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs (JZ, IS, AJ), pp. 1035–1040.
DATE-2010-YangGBSC #automation: Automated bottleneck-driven design-space exploration of media processing systems (YY, MG, TB, SS, HC), pp. 1041–1046.
DATE-2010-DammMHG #modelling #network #simulation #transaction #using: Using Transaction Level Modeling techniques for wireless sensor network simulation (MD, JM, JH, CG), pp. 1047–1052.
DATE-2010-BeckerGF0PX #design #refinement: RTOS-aware refinement for TLM2.0-based HW/SW designs (MB, GDG, FF, WM, GP, TX), pp. 1053–1058.
DATE-2010-LiSBNO #analysis #implementation: Power Variance Analysis breaks a masked ASIC implementation of AES (YL, KS, LB, DN, KO), pp. 1059–1064.
DATE-2010-WangT #novel #physics #process: Novel Physical Unclonable Function with process and environmental variations (XW, MT), pp. 1065–1070.
DATE-2010-VenutoSCP #power management: Ultra low-power 12-bit SAR ADC for RFID applications (DDV, ES, DTC, YP), pp. 1071–1075.
DATE-2010-CutrupiCCG #detection #flexibility: A flexible UWB Transmitter for breast cancer detection imaging systems (MC, MC, MRC, MG), pp. 1076–1081.
DATE-2010-LoHCHC #flexibility #multi: A portable multi-pitch e-drum based on printed flexible pressure sensors (CML, TCH, CYC, JH, KTC), pp. 1082–1087.
DATE-2010-Mueller-GritschnederG #specification: Computation of yield-optimized Pareto fronts for analog integrated circuit specifications (DMG, HG), pp. 1088–1093.
DATE-2010-MaricauG #complexity #reliability #simulation #variability: Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity (EM, GGEG), pp. 1094–1099.
DATE-2010-LauLCB #probability: A general mathematical model of probabilistic ripple-carry adders (MSKL, KVL, YCC, AB), pp. 1100–1105.
DATE-2010-LiuFG #optimisation #performance: An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique (BL, FVF, GGEG), pp. 1106–1111.
DATE-2010-WangXY #scheduling: Reuse-aware modulo scheduling for stream processors (LW, JX, XY), pp. 1112–1117.
DATE-2010-ChePC #compilation #manycore #source code: Compilation of stream programs for multicore processors that incorporate scratchpad memories (WC, AP, KSC), pp. 1118–1123.
DATE-2010-TakaseTT #clustering #memory management #multi: Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems (HT, HT, HT), pp. 1124–1129.
DATE-2010-ZhangDYMZKCPS #code generation #compilation #evaluation: A special-purpose compiler for look-up table and code generation for function evaluation (YZ, LD, PY, SPM, HZ, MTK, CC, NP, XS), pp. 1130–1135.
DATE-2010-EguiaTSPT #behaviour #design #manycore #modelling: General behavioral thermal modeling and characterization for multi-core microprocessor design (TJAE, SXDT, RS, EHP, MT), pp. 1136–1141.
DATE-2010-ChineaGDDK #megamodelling #on the #performance: On the construction of guaranteed passive macromodels for high-speed channels (AC, SGT, DD, TD, LK), pp. 1142–1147.
DATE-2010-YeSP #assessment: Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systems (ZY, LMS, JRP), pp. 1148–1152.
DATE-2010-WatanabeA #modelling #multi #performance #simulation: Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation (TW, HA), pp. 1153–1158.
DATE-2010-ZhangPLWM: Carbon nanotube circuits: Living with imperfections and variations (JZ, NP, AL, HSPW, SM), pp. 1159–1164.
DATE-2010-ChenDS #algorithm #analysis: Properties of and improvements to time-domain dynamic thermal analysis algorithms (XC, RPD, LS), pp. 1165–1170.
DATE-2010-LammermannRKRVJH #design #towards #verification: Towards assertion-based verification of heterogeneous system designs (SL, JR, TK, WR, AV, AJ, LH), pp. 1171–1176.
DATE-2010-WuLCT #abstraction #automation #generative #multi #performance: Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation (MHW, WCL, CYC, RST), pp. 1177–1182.
DATE-2010-KhalighR #adaptation #kernel #modelling #parallel #simulation: Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs (RSK, MR), pp. 1183–1188.
DATE-2010-ZebeleinFHTD #modelling #network #performance: Efficient High-Level modeling in the networking domain (CZ, JF, CH, JT, RD), pp. 1189–1194.
DATE-2010-VidalLGDS #configuration management #design #embedded #multi #uml: UML design for dynamically reconfigurable multiprocessor embedded systems (JV, FdL, GG, JPD, PS), pp. 1195–1200.
DATE-2010-MischkallaH0 #modelling #simulation #synthesis #uml: Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems (FM, DH, WM), pp. 1201–1206.
DATE-2010-FerroP #modelling #semantics #transaction #verification: Formal semantics for PSL modeling layer and application to the verification of transactional models (LF, LP), pp. 1207–1212.
DATE-2010-Pignol: COTS-based applications in space avionics (MP), pp. 1213–1219.
DATE-2010-BauerSF #analysis #network #worst-case: Worst-case end-to-end delay analysis of an avionics AFDX network (HB, JLS, CF), pp. 1220–1224.
DATE-2010-SarnoT #integration: Integration, cooling and packaging issues for aerospace equipments (CS, CT), pp. 1225–1230.
DATE-2010-SterponeB #algorithm #multi: A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs (LS, NB), pp. 1231–1236.
DATE-2010-PomeranzR #requirements #sequence #testing #using: Reducing the storage requirements of a test sequence by using a background vector (IP, SMR), pp. 1237–1242.
DATE-2010-ElmW #named #self: BISD: Scan-based Built-In self-diagnosis (ME, HJW), pp. 1243–1248.
DATE-2010-Mirza-AghatabarBG #algorithm #pipes and filters: Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules (MMA, MAB, SKG), pp. 1249–1254.
DATE-2010-CongHJ #algorithm #behaviour #pattern matching #pattern recognition #recognition #synthesis: A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis (JC, HH, WJ), pp. 1255–1260.
DATE-2010-YuZQB #behaviour #design #power management: Behavioral level dual-vth design for reduced leakage power with thermal awareness (JY, QZ, GQ, JB), pp. 1261–1266.
DATE-2010-CongLX #behaviour #coordination #optimisation #synthesis: Coordinated resource optimization in behavioral synthesis (JC, BL, JX), pp. 1267–1272.
DATE-2010-BanerjeeASNO #design: A methodology for propagating design tolerances to shape tolerances for use in manufacturing (SB, KBA, CNS, SRN, MO), pp. 1273–1278.
DATE-2010-GaoM #lazy evaluation: Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance (XG, LM), pp. 1279–1284.
DATE-2010-HatamiP #analysis #component #library #performance #representation #robust #using: Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis (SH, MP), pp. 1285–1290.
DATE-2010-LiSC #logic #manycore: Exploiting local logic structures to optimize multi-core SoC floorplanning (CHL, SS, LPC), pp. 1291–1296.
DATE-2010-HaastregtHK #cost analysis #modelling #multi: Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems (SvH, EH, BK), pp. 1297–1300.
DATE-2010-LomneDMTR #analysis #difference #preprocessor #statistics: Differential Power Analysis enhancement with statistical preprocessing (VL, AD, PM, LT, MR), pp. 1301–1304.
DATE-2010-JaffariA10a #analysis #correlation #performance #variability: Correlation controlled sampling for efficient variability analysis of analog circuits (JJ, MA), pp. 1305–1308.
DATE-2010-NarayananAZTP #process #verification: Formal verification of analog circuits in the presence of noise and process variation (RN, BA, MHZ, ST, LCP), pp. 1309–1312.
DATE-2010-CharfiMGTB #code generation #modelling #optimisation #towards: Toward optimized code generation through model-based optimization (AC, CM, SG, FT, PB), pp. 1313–1316.
DATE-2010-GuFP #compilation #hardware #scheduling: Path-based scheduling in a hardware compiler (RG, AF, RNP), pp. 1317–1320.
DATE-2010-ChengLW #diagrams #optimisation: Optimization of FIR filter to improve eye diagram for general transmission line systems (YSC, YCL, RBW), pp. 1321–1324.
DATE-2010-WeerasekeraGPT #3d #on the: On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits (RW, MG, DP, HT), pp. 1325–1328.
DATE-2010-ZengC #metric #using: Interconnect delay and slew metrics using the beta distribution (JKZ, CPC), pp. 1329–1332.
DATE-2010-HwangSAG #modelling #transaction: Accurate timed RTOS model for transaction level modeling (YH, GS, SA, DDG), pp. 1333–1336.
DATE-2010-OnoTKSNF #evaluation #execution #modelling #performance: A modeling method by eliminating execution traces for performance evaluation (KO, MT, RK, YS, TN, NF), pp. 1337–1340.
DATE-2010-SoekenWKGD #modelling #ocl #satisfiability #uml #using #verification: Verifying UML/OCL models using Boolean satisfiability (MS, RW, MK, MG, RD), pp. 1341–1344.
DATE-2010-KoebelC #named: SCOC3: a space computer on a chip (FK, JFC), pp. 1345–1348.
DATE-2010-LandrockK: High temperature polymer capacitors for aerospace applications (CKL, BK), pp. 1349–1352.
DATE-2010-PeiLL #generative #testing: An on-chip clock generation scheme for faster-than-at-speed delay testing (SP, HL, XL), pp. 1353–1356.
DATE-2010-EconomakosXKS #component #configuration management #synthesis: Construction of dual mode components for reconfiguration aware high-level synthesis (GE, SX, IK, DS), pp. 1357–1360.
DATE-2010-PerezSF #data flow #graph #optimisation #relational: Optimizing Data-Flow Graphs with min/max, adding and relational operations (JP, PS, VF), pp. 1361–1364.
DATE-2010-LongM #bias #monitoring #network #optimisation: Optimization of the bias current network for accurate on-chip thermal monitoring (JL, SOM), pp. 1365–1368.
DATE-2010-YangCZH #multi #satisfiability: SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal (FY, YC, QZ, JH), pp. 1369–1372.
DATE-2010-AlpaslanDKMHW #simulation: NIM- a noise index model to estimate delay discrepancies between silicon and simulation (EA, JD, BK, AKM, WMH, PvdW), pp. 1373–1376.
DATE-2010-Jerger #named: SigNet: Network-on-chip filtering for coarse vector directories (NDEJ), pp. 1378–1383.
DATE-2010-SharifiZK #feedback #multi: Feedback control for providing QoS in NoC based multicores (AS, HZ, MTK), pp. 1384–1389.
DATE-2010-JunYC #library #multi #network #synthesis: Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network (MJ, SY, EYC), pp. 1390–1395.
DATE-2010-CupaiuoloST #architecture #detection #ml #throughput: Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector (TC, MS, AT), pp. 1396–1401.
DATE-2010-PakerEB #algorithm #architecture #low cost #multi #standard: A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architecture (ÖP, SE, AB), pp. 1402–1407.
DATE-2010-BerahaWCK #case study #design #requirements: Leveraging application-level requirements in the design of a NoC for a 4G SoC — a case study (RB, IW, IC, AK), pp. 1408–1413.
DATE-2010-ZhangLZMC #architecture #communication #generative: Domain specific architecture for next generation wireless communication (BZ, HL, HZ, FM, TC), pp. 1414–1419.
DATE-2010-MayIWR: A 150Mbit/s 3GPP LTE Turbo code decoder (MM, TI, NW, WR), pp. 1420–1425.
DATE-2010-PengYTC #fault #process: High-quality pattern selection for screening small-delay defects considering process variations and crosstalk (KP, MY, MT, KC), pp. 1426–1431.
DATE-2010-LiuZYX #power management #pseudo #testing: Layout-aware pseudo-functional testing for critical paths considering power supply noise effects (XL, YZ, FY, QX), pp. 1432–1437.
DATE-2010-PomeranzR10a #functional #on the #testing: On reset based functional broadside tests (IP, SMR), pp. 1438–1443.
DATE-2010-LiuLW #energy #fault tolerance #performance #realtime #scheduling: Scheduling for energy efficiency and fault tolerance in hard real-time systems (YL, HL, KW), pp. 1444–1449.
DATE-2010-SheaSC #identifier #performance: Scoped identifiers for efficient bit aligned logging (RS, MBS, YC), pp. 1450–1455.
DATE-2010-FerentSGD #approach #embedded #linear #network #programming: Linear programming approach for performance-driven data aggregation in networks of embedded sensors (CF, VS, MG, AD), pp. 1456–1461.
DATE-2010-ShafikAC #design #embedded #optimisation #power management: Soft error-aware design optimization of low power and time-constrained embedded systems (RAS, BMAH, KC), pp. 1462–1467.
DATE-2010-LeeM #named #network #optimisation: Contango: Integrated optimization of SoC clock networks (DL, ILM), pp. 1468–1473.
DATE-2010-LungZCC #optimisation: Clock skew optimization considering complicated power modes (CLL, ZYZ, CHC, SCC), pp. 1474–1479.
DATE-2010-SuCG #multi: A general method to make multi-clock system deterministic (MS, YC, XG), pp. 1480–1485.
DATE-2010-Cota #embedded #problem #question #testing #what: Embedded software testing: What kind of problem is this? (ÉFC), p. 1486.
DATE-2010-Antoniadis #challenge: Nanoelectronics challenges for the 21st century (DA), p. 1487.
DATE-2010-LeupersTNKWI #programming: Cool MPSoC programming (RL, LT, XN, BK, MW, TI), pp. 1488–1493.
DATE-2010-ChouYCDK #case study #design #nondeterminism #scalability: Finding reset nondeterminism in RTL designs — scalable X-analysis methodology and case study (HZC, HY, KHC, DD, SYK), pp. 1494–1499.
DATE-2010-HaoXRY #behaviour #equivalence #optimisation #synthesis: Optimizing equivalence checking for behavioral synthesis (KH, FX, SR, JY), pp. 1500–1505.
DATE-2010-RaffelsieperMS #library: Checking and deriving module paths in Verilog cell library descriptions (MR, MRM, CWHS), pp. 1506–1511.
DATE-2010-BuLWCL #bound #composition #hybrid #linear #reachability: BACH 2 : Bounded reachability checker for compositional linear hybrid systems (LB, YL, LW, XC, XL), pp. 1512–1517.
DATE-2010-RavinagarajanDR #health #monitoring #scheduling: DVFS based task scheduling in a harvesting WSN for Structural Health Monitoring (AR, DD, TSR), pp. 1518–1523.
DATE-2010-BoydSS #detection #process #trade-off: Power-accuracy tradeoffs in human activity transition detection (JB, HS, AS), pp. 1524–1529.
DATE-2010-ChenABF #monitoring #using: Non-invasive blood oxygen saturation monitoring for neonates using reflectance pulse oximeter (WC, IA, SBO, LMGF), pp. 1530–1535.
DATE-2010-DiracoLS #detection #recognition: An active vision system for fall detection and posture recognition in elderly healthcare (GD, AL, PS), pp. 1536–1541.
DATE-2010-VergariBSDZRC: A Smart Space application to dynamically relate medical and environmental information (FV, SB, FS, AD, GZ, LR, TSC), pp. 1542–1547.
DATE-2010-SyedLF #architecture #pervasive #self: An architecture for self-organization in pervasive systems (AAS, JL, RF), pp. 1548–1553.
DATE-2010-ChoudhuryCMA10a #fault #named #online: TIMBER: Time borrowing and error relaying for online timing error resilience (MRC, VC, KM, RCA), pp. 1554–1559.
DATE-2010-LeemCBJM #architecture #fault #named #probability: ERSA: Error Resilient System Architecture for probabilistic applications (LL, HC, JB, QAJ, SM), pp. 1560–1565.
DATE-2010-ZhangYDHRL #manycore #symmetry: Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors (LZ, YY, JD, YH, SR, XL), pp. 1566–1571.
DATE-2010-SubramanyanSSL #execution #fault tolerance #multi #performance: Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors (PS, VS, KKS, EL), pp. 1572–1577.
DATE-2010-LukasiewyczGT #design #embedded #robust: Robust design of embedded systems (ML, MG, JT), pp. 1578–1583.
DATE-2010-HuangX10a #constraints #energy #multi #reliability #scheduling: Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint (LH, QX), pp. 1584–1589.
DATE-2010-ChenYW #memory management #named: PM-COSYN: PE and memory co-synthesis for MPSoCs (YJC, CLY, PHW), pp. 1590–1595.
DATE-2010-MeyerHT #effectiveness: Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs (BHM, ASH, DET), pp. 1596–1601.
DATE-2010-LuPRR #energy #performance #transducer: Efficient power conversion for ultra low voltage micro scale energy transducers (CL, SPP, VR, KR), pp. 1602–1607.
DATE-2010-SchulzBUES #modelling #transaction: Transmitting TLM transactions over analogue wire models (SS, JB, TU, KE, SS), pp. 1608–1613.
DATE-2010-JeeraditKH #optimisation: Intent-leveraged optimization of analog circuits via homotopy (MJ, JK, MH), pp. 1614–1619.
DATE-2010-JafariLJY: Optimal regulation of traffic flows in networks-on-chip (FJ, ZL, AJ, MHY), pp. 1621–1624.
DATE-2010-SeiculescuMBM: A method to remove deadlocks in Networks-on-Chips with Wormhole flow control (CS, SM, LB, GDM), pp. 1625–1628.
DATE-2010-ForoutanTHJ #performance: An analytical method for evaluating Network-on-Chip performance (SF, YT, RH, AJ), pp. 1629–1632.
DATE-2010-Moezzi-MadaniTD #detection #flexibility #standard: A low-area flexible MIMO detector for WiFi/WiMAX standards (NMM, TT, WRD), pp. 1633–1636.
DATE-2010-LeeYCC #embedded #metric: An embedded wide-range and high-resolution CLOCK jitter measurement circuit (YL, CYY, NCDC, JJC), pp. 1637–1640.
DATE-2010-GomezSBF: Analog circuit test based on a digital signature (AG, RS, LB, JF), pp. 1641–1644.
DATE-2010-IqbalSH10a #estimation #execution #graph #monte carlo #named: DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation (NI, MAS, JH), pp. 1645–1648.
DATE-2010-DixitDR #component #embedded #realtime: Taming the component timing: A CBD methodology for real-time embedded systems (MGD, PD, SR), pp. 1649–1652.
DATE-2010-AndalamRG #multi #predict #thread #using: Deterministic, predictable and light-weight multithreading using PRET-C (SA, PSR, AG), pp. 1653–1656.
DATE-2010-LongM10a #dependence #scheduling: Inversed Temperature Dependence aware clock skew scheduling for sequential circuits (JL, SOM), pp. 1657–1660.
DATE-2010-AgheraKFCR #energy #named #performance: DynAHeal: Dynamic energy efficient task assignment for wireless healthcare systems (PA, DK, DF, AKC, TR), pp. 1661–1664.
DATE-2010-BorodinJ #detection #fault: Instruction precomputation with memoization for fault detection (DB, BHHJ), pp. 1665–1668.
DATE-2010-WiggersBGB #graph: Simultaneous budget and buffer size computation for throughput-constrained task graphs (MW, MB, MG, TB), pp. 1669–1672.
DATE-2010-PanYZS #approach #megamodelling #order #performance #reduction: An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits (XP, FY, XZ, YS), pp. 1673–1676.
DATE-2010-KlumppRW #3d: 3D-integration of silicon devices: A key technology for sophisticated products (AK, PR, RW), pp. 1678–1683.
DATE-2010-FranzonDT #3d #architecture #design: Creating 3D specific systems: Architecture, design and CAD (PDF, WRD, TT), pp. 1684–1688.
DATE-2010-Marinissen #3d #testing: Testing TSV-based three-dimensional stacked ICs (EJM), pp. 1689–1694.
DATE-2010-MangassarianLGVB #preprocessor: Leveraging dominators for preprocessing QBF (HM, BL, AG, AGV, FB), pp. 1695–1700.
DATE-2010-VerbeekS #concurrent #specification: Formal specification of networks-on-chips: deadlock and evacuation (FV, JS), pp. 1701–1706.
DATE-2010-CimattiFGKR #abstraction #integration #smt: Tighter integration of BDDs and SMT for Predicate Abstraction (AC, AF, AG, KK, MR), pp. 1707–1712.
DATE-2010-ShafiqueMH #adaptation #complexity #reduction #using #video: An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion (MS, BM, JH), pp. 1713–1718.
DATE-2010-AnastasiaA #energy #image #refinement #scheduling #trade-off: Scheduling and energy-distortion tradeoffs with operational refinement of image processing (DA, YA), pp. 1719–1724.
DATE-2010-ShafiqueBH #adaptation #energy #estimation #named #predict #runtime #video: enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder (MS, LB, JH), pp. 1725–1730.
DATE-2010-VasicekSB #design #implementation: A method for design of impulse bursts noise filters optimized for FPGA implementations (ZV, LS, MB), pp. 1731–1736.
DATE-2010-LopezSPLC #hardware #image: Exploration of hardware sharing for image encoders (SL, RS, PGP, WL, PYKC), pp. 1737–1742.
DATE-2010-HadjitheophanousTGT #3d #hardware #re-engineering #realtime #towards: Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map (SH, CT, ASG, TT), pp. 1743–1748.
DATE-2010-HuangCLH #robust: A robust ADC code hit counting technique (JLH, KYC, MHL, XLH), pp. 1749–1754.
DATE-2010-AbbasCFKA #adaptation #automation #framework #generative #performance #testing: An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links (MA, KTC, YF, SK, KA), pp. 1755–1760.
DATE-2010-HuangSM #fault #machine learning: Fault diagnosis of analog circuits based on machine learning (KH, HGDS, SM), pp. 1761–1766.
DATE-2010-KrishnanDBK: Block-level bayesian diagnosis of analogue electronic circuits (SK, KDD, RB, HGK), pp. 1767–1772.
DATE-2010-KiladaS #design #generative #latency #network: Control network generator for latency insensitive designs (EK, KSS), pp. 1773–1778.
DATE-2010-BarrioMMHM #functional #synthesis #using: Using Speculative Functional Units in high level synthesis (AADB, MCM, JMM, RH, SOM), pp. 1779–1784.
DATE-2010-Zhu #algorithm #multi #realtime: Retiming multi-rate DSP algorithms to meet real-time requirement (XYZ), pp. 1785–1790.
DATE-2010-LiuTL #automation #design #optimisation #power management: Combining optimizations in automated low power design (QL, TT, WL), pp. 1791–1796.
DATE-2010-LazzariFMC #multi: A new quaternary FPGA based on a voltage-mode multi-valued circuit (CL, PFF, JM, LC), pp. 1797–1802.
DATE-2010-GupteJ #evaluation #fault #slicing: An evaluation of a slice fault aware tool chain (AG, PHJ), pp. 1803–1808.
DATE-2010-BsoulMS #process: Reliability- and process variation-aware placement for FPGAs (AAMB, NM, LS), pp. 1809–1814.

Proceedings of the 14th Conference on Design, Automation and Test in EuropeDATE, 2010.

Contents (344 items)

Proceedings of the 14th Conference on Design, Automation and Test in Europe
DATE, 2010.