Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
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Luciano Bononi, Nicola Concer
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
DATE, 2006.

DATE DF 2006
DBLP
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@inproceedings{DATE-DF-2006-BononiC,
	author        = "Luciano Bononi and Nicola Concer",
	booktitle     = "{Proceedings of the 10th Conference on Design, Automation and Test in Europe: Designers’ Forum}",
	doi           = "10.1145/1131355.1131388",
	isbn          = "3-9810801-0-6",
	pages         = "154--159",
	publisher     = "{European Design and Automation Association, Leuven, Belgium}",
	title         = "{Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh}",
	year          = 2006,
}

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