BibSLEIGH — Proceedings of the 10th Conference on Design, Automation and Test in Europe: Designers’ Forum

Georges G. E. Gielen
Proceedings of the 10th Conference on Design, Automation and Test in Europe: Designers’ Forum
DATE Designers’ Forum, 2006.

SYS

@proceedings{DATE-DF-2006,
	address       = "Munich, Germany",
	editor        = "Georges G. E. Gielen",
	isbn          = "3-9810801-0-6",
	publisher     = "{European Design and Automation Association, Leuven, Belgium}",
	title         = "{Proceedings of the 10th Conference on Design, Automation and Test in Europe: Designers’ Forum}",
	year          = 2006,
}

Contents (45 items)

DATE-DF-2006-AarajRRJ #architecture #authentication #embedded #performance: Architectures for efficient face authentication in embedded systems (NA, SR, AR, NKJ), pp. 1–6.
DATE-DF-2006-BertoniBFPS #implementation: Software implementation of Tate pairing over GF(2m) (GB, LB, PF, GP, LS), pp. 7–11.
DATE-DF-2006-LinHJC #optimisation #pattern matching #regular expression: Optimization of regular expression pattern matching circuits on FPGA (CHL, CTH, CPJ, SCC), pp. 12–17.
DATE-DF-2006-PotlapallyRRJL #encryption #framework #satisfiability: Satisfiability-based framework for enabling side-channel attacks on cryptographic software (NRP, AR, SR, NKJ, RBL), pp. 18–23.
DATE-DF-2006-YehHCWC #design: An 830mW, 586kbps 1024-bit RSA chip design (CY, EFH, KWC, JSW, NJC), pp. 24–29.
DATE-DF-2006-AkselrodAA #architecture #debugging #framework #independence #multi #platform #security: Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs (DA, AA, YA), pp. 30–35.
DATE-DF-2006-VeredasSP #automation #performance: Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time (FJV, MS, HJP), pp. 36–41.
DATE-DF-2006-MeijerKB #design #energy: Energy-efficient FPGA interconnect design (MM, RK, MTB), pp. 42–47.
DATE-DF-2006-MartinaMMVSV #approach #programmable: A new approach to compress the configuration information of programmable devices (MM, GM, AM, FV, LS, MV), pp. 48–51.
DATE-DF-2006-DavilaTSSBR #algorithm #architecture #configuration management #design #implementation: Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys) (JD, AdT, JMS, MSE, NB, FR), pp. 52–57.
DATE-DF-2006-KappenN #implementation: Application specific instruction processor based implementation of a GNSS receiver on an FPGA (GK, TGN), pp. 58–63.
DATE-DF-2006-HuttonYSBCCP #synthesis #verification: A methodology for FPGA to structured-ASIC synthesis and verification (MH, RY, JS, GB, SC, KKC, HKP), pp. 64–69.
DATE-DF-2006-DasMDC #synthesis: Synthesis of system verilog assertions (SD, RM, PD, PPC), pp. 70–75.
DATE-DF-2006-HabibiMT #finite #generative #state machine: Generating finite state machines from SystemC (AH, HM, ST), pp. 76–81.
DATE-DF-2006-OetjensGR #design #flexibility #rule-based #specification: Flexible specification and application of rule-based transformations in an automotive design flow (JHO, JG, WR), pp. 82–87.
DATE-DF-2006-BonfiniCMP #verification: A mixed-signal verification kit for verification of analogue-digital circuits (GB, MC, RM, EP), pp. 88–93.
DATE-DF-2006-Daglio #design #embedded #verification: A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memories (PD), pp. 94–99.
DATE-DF-2006-NogueraBSA #case study #industrial: Software-friendly HW/SW co-simulation: an industrial case study (JN, LB, NS, LA), pp. 100–105.
DATE-DF-2006-FummiQRT #mobile #modelling #network #simulation: Modeling and simulation of mobile gateways interacting with wireless sensor networks (FF, DQ, FR, MT), pp. 106–111.
DATE-DF-2006-PapaefstathiouP #classification: A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments (VP, IP), pp. 112–117.
DATE-DF-2006-IaconoZMPSB #architecture #multi #standard: ASIP architecture for multi-standard wireless terminals (DLI, JZ, EM, NP, GS, AB), pp. 118–123.
DATE-DF-2006-QuaglioVCTM #flexibility #framework: Interconnection framework for high-throughput, flexible LDPC decoders (FQ, FV, CC, AT, GM), pp. 124–129.
DATE-DF-2006-DielissenHB #low cost: Low cost LDPC decoder for DVB-S2 (JD, AH, VB), pp. 130–135.
DATE-DF-2006-SamaPFBR #3d #low cost #named #power management: 3dID: a low-power, low-cost hand motion capture device (MS, VP, EF, LB, BR), pp. 136–141.
DATE-DF-2006-LennardBFIUSWFRB #design #integration #proving #specification: Industrially proving the SPIRIT consortium specifications for design chain integration (CKL, VB, SF, MI, CU, MS, JW, OF, FR, PB), pp. 142–147.
DATE-DF-2006-SteenhofDNGL #architecture #network: Networks on chips for high-end consumer-electronics TV system architectures (FS, HD, BN, KG, RPL), pp. 148–153.
DATE-DF-2006-BononiC #2d #analysis #architecture #network #simulation: Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh (LB, NC), pp. 154–159.
DATE-DF-2006-CampobelloCCM #network: GALS networks on chip: a new solution for asynchronous delay-insensitive links (GC, MC, CC, DM), pp. 160–165.
DATE-DF-2006-DumitrascuBPBJ #flexibility #framework #performance #platform: Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application (FD, IB, LP, MB, AAJ), pp. 166–171.
DATE-DF-2006-NazarianPGB #named #set #statistics: STAX: statistical crosstalk target set compaction (SN, MP, SKG, MAB), pp. 172–177.
DATE-DF-2006-ChengL #multi: A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs (KHC, YLL), pp. 178–182.
DATE-DF-2006-RichterE #challenge #how #integration #network: How OEMs and suppliers can face the network integration challenges (KR, RE), pp. 183–188.
DATE-DF-2006-CarvalhoPJF #algorithm #fault tolerance #implementation: A practical implementation of the fault-tolerant daisy-chain clock synchronization algorithm on CAN (FCC, CEP, ETSJ, EPdF), pp. 189–194.
DATE-DF-2006-ZarriCDMPRT #on the #protocol #verification: On the verification of automotive protocols (GZ, FC, FD, RM, MP, GR, CT), pp. 195–200.
DATE-DF-2006-BarontiDKMRSSSV: FlexRay transceiver in a 0.35 µm CMOS high-voltage technology (FB, PD, MK, RM, RR, RS, MS, RS, VV), pp. 201–205.
DATE-DF-2006-RaabeHAZ #detection #prototype: Space-efficient FPGA-accelerated collision detection for virtual prototyping (AR, SH, JKA, GZ), pp. 206–211.
DATE-DF-2006-SaponaraT #design: Mixed-signal design of a digital input power amplifier for automotive audio applications (SS, PT), pp. 212–216.
DATE-DF-2006-BannowHR #automation #clustering #design #evaluation #performance: Automatic systemC design configuration for a faster evaluation of different partitioning alternatives (NB, KH, WR), pp. 217–218.
DATE-DF-2006-SerafiniCRZ #configuration management #framework #multi #platform: Multi-sensor configurable platform for automotive applications (LS, FC, TR, VZ), pp. 219–220.
DATE-DF-2006-KaruriLAMK #composition #design #float #implementation: Design and implementation of a modular and portable IEEE 754 compliant floating-point unit (KK, RL, GA, HM, MK), pp. 221–226.
DATE-DF-2006-ArifinC #adaptation #clustering #implementation #logic #novel #segmentation: A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation (SA, PYKC), pp. 227–232.
DATE-DF-2006-FanucciCSKWSALM #design #image #linear #synthesis: ASIP design and synthesis for non linear filtering in image processing (LF, MC, SS, DK, EMW, OS, GA, RL, HM), pp. 233–238.
DATE-DF-2006-YehWLW #multi #programmable: A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications (CY, CCW, LCL, JSW), pp. 239–243.
DATE-DF-2006-MadingLPSBEH #architecture #fixpoint: The vector fixed point unit of the synergistic processor element of the cell architecture processor (NM, JL, JP, RS, SB, SE, WH), pp. 244–248.
DATE-DF-2006-SohnWYY #design #fixpoint #mobile #multi: Design and test of fixed-point multimedia co-processor for mobile applications (JHS, JHW, JY, HJY), pp. 249–253.

Georges G. E. GielenProceedings of the 10th Conference on Design, Automation and Test in Europe: Designers’ ForumDATE Designers’ Forum, 2006.

Contents (45 items)

Georges G. E. Gielen
Proceedings of the 10th Conference on Design, Automation and Test in Europe: Designers’ Forum
DATE Designers’ Forum, 2006.