BibSLEIGH — chip stem

Used together with:

network (196)
system (183)
design (133)
base (88)
power (77)

Stem chip$ (all stems)

745 papers:

DAC-2015-BokhariJSHP #architecture #manycore #named: SuperNet: multimode interconnect architecture for manycore chips (HB, HJ, MS, JH, SP), p. 6.
DAC-2015-CongGHRY #architecture #network: On-chip interconnection network for accelerator-rich architectures (JC, MG, YH, GR, BY), p. 6.
DAC-2015-JangKGY0 #design: Bandwidth-efficient on-chip interconnect designs for GPGPUs (HJ, JK, PG, KHY, EJK), p. 6.
DAC-2015-KhdrPSH #resource management: Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips (HK, SP, MS, JH), p. 6.
DAC-2015-LiBTO #communication #energy #performance: Complementary communication path for energy efficient on-chip optical interconnects (HL, SLB, YT, IO), p. 6.
DAC-2015-LiuSZLQ #generative #statistics: A statistical methodology for noise sensor placement and full-chip voltage map generation (XL, SS, PZ, XL, HQ), p. 6.
DAC-2015-ShafiqueKTH #anti #energy #named #video: EnAAM: energy-efficient anti-aging for on-chip video memories (MS, MUKK, AOT, JH), p. 6.
DAC-2015-YangCK #design: Virtual flash chips: rethinking the layer design of flash devices to improve data recoverability (MCY, YHC, TWK), p. 6.
DAC-2015-YuUK: Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks (WY, OAU, SK), p. 6.
DAC-2015-ZhanOGZ0 #approach #named #network #power management #towards: DimNoC: a dim silicon approach towards power-efficient on-chip network (JZ, JO, FG, JZ, YX), p. 6.
DATE-2015-BalboniFB #configuration management #distributed #latency #multi #network #scalability: Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration (MB, JF, DB), pp. 806–811.
DATE-2015-BokhariJSHP #adaptation: Malleable NoC: dark silicon inspired adaptable Network-on-Chip (HB, HJ, MS, JH, SP), pp. 1245–1248.
DATE-2015-ChenKXMLYVSCY #algorithm #array #learning: Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip (PYC, DK, ZX, AM, BL, JY, SBKV, JsS, YC, SY), pp. 854–859.
DATE-2015-ChenZWWWZ #multi #named #pseudo #simulation: MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation (XC, GZ, HW, RW, PW, LZ), pp. 211–216.
DATE-2015-ErolOSPB #metric #using: On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC (OEE, SO, CKHS, RAP, LB), pp. 1559–1562.
DATE-2015-KarkarTMY #communication #distributed #multi: Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting (AK, KFT, TSTM, AY), pp. 794–799.
DATE-2015-LaerEMWJ #multi #predict: Coherence based message prediction for optically interconnected chip multiprocessors (AVL, CE, MRM, PMW, TMJ), pp. 613–616.
DATE-2015-LiFBLON #design: Thermal aware design method for VCSEL-based on-chip optical interconnect (HL, AF, SLB, XL, IO, GN), pp. 1120–1125.
DATE-2015-MajumderPK #architecture #biology #manycore: On-chip network-enabled many-core architectures for computational biology applications (TM, PPP, AK), pp. 259–264.
DATE-2015-MazloumiM #hybrid #memory management #multi: A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors (AM, MM), pp. 908–911.
DATE-2015-MirhosseiniSFMS #energy #network: An energy-efficient virtual channel power-gating mechanism for on-chip networks (AM, MS, AF, MM, HSA), pp. 1527–1532.
DATE-2015-RamboE #analysis #communication #worst-case: Worst-case communication time analysis of networks-on-chip with shared virtual channels (EAR, RE), pp. 537–542.
DATE-2015-RenTB #detection #learning #statistics: Detection of illegitimate access to JTAG via statistical learning in chip (XR, VGT, RD(B), pp. 109–114.
DATE-2015-SarmaDGVN #paradigm #self: Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation (SS, NDD, PG, NV, AN), pp. 625–628.
DATE-2015-ShafiqueGGH #manycore #variability: Variability-aware dark silicon management in on-chip many-core systems (MS, DG, SG, JH), pp. 387–392.
TACAS-2015-KriouileS #formal method #using #verification: Using a Formal Model to Improve Verification of a Cache-Coherent System-on-Chip (AK, WS), pp. 708–722.
PLDI-2015-DingTKZK #multi #optimisation: Optimizing off-chip accesses in multicores (WD, XT, MTK, YZ, EK), pp. 131–142.
PLDI-2015-LongfieldNMT #self #specification: Preventing glitches and short circuits in high-level self-timed chip specifications (SLJ, BN, RM, RT), pp. 270–279.
FM-2015-KuritaIA #documentation #evolution #formal method #mobile #modelling: Practices for Formal Models as Documents: Evolution of VDM Application to “Mobile FeliCa” IC Chip Firmware (TK, FI, KA), pp. 593–596.
CGO-2015-LiYLZ #automation #gpu #memory management: Automatic data placement into GPU on-chip memory resources (CL, YY, ZL, HZ), pp. 23–33.
HPCA-2015-DuweJ0 #fault #latency #predict: Correction prediction: Reducing error correction latency for on-chip memories (HD, XJ, RK), pp. 463–475.
HPCA-2015-WangPBAK #alloy #architecture #memory management #named: Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems (HW, CJP, GB, JHA, NSK), pp. 296–308.
DAC-2014-AhnYC #hybrid #memory management #power management: Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes (JA, SY, KC), p. 6.
DAC-2014-AlbalawiLL #algorithm #classification #design #fixpoint #implementation #machine learning #power management: Computer-Aided Design of Machine Learning Algorithm: Training Fixed-Point Classifier for On-Chip Low-Power Implementation (HA, YL, XL), p. 6.
DAC-2014-BokhariJSHP #design #energy #multi #named: darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon (HB, HJ, MS, JH, SP), p. 6.
DAC-2014-GuinZFT #low cost: Low-cost On-Chip Structures for Combating Die and IC Recycling (UG, XZ, DF, MT), p. 6.
DAC-2014-KoestersG #verification: Verification of Non-Mainline Functions in Todays Processor Chips (JK, AG), p. 3.
DAC-2014-Kose #challenge: Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible Solutions (SK), p. 6.
DAC-2014-LiuHM #detection #hardware #statistics: Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting (YL, KH, YM), p. 6.
DAC-2014-PengPL #optimisation #performance: Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling (YP, DP, SKL), p. 6.
DAC-2014-RenMRZ #fault tolerance #network #using: Fault-tolerant Routing for On-chip Network Without Using Virtual Channels (PR, QM, XR, NZ), p. 6.
DAC-2014-XueQBYT #analysis #framework #manycore #scalability: Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis (YX, ZQ, PB, FY, CYT), p. 6.
DAC-2014-ZhengBB #analysis #identification #named #robust #towards: CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification (YZ, AB, SB), p. 6.
DATE-2014-BahrebarS #approach #network: Improving hamiltonian-based routing methods for on-chip networks: A turn model approach (PB, DS), pp. 1–4.
DATE-2014-BeneventiBVDB #analysis #identification #logic: Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip (FB, AB, PV, DD, LB), pp. 1–4.
DATE-2014-BeuxLOCLTN #named #performance: Chameleon: Channel efficient Optical Network-on-Chip (SLB, HL, IO, KC, XL, JT, GN), pp. 1–6.
DATE-2014-Bolle #roadmap: The connected car and its implication to the automotive chip roadmap (MB), p. 1.
DATE-2014-DamodaranWH #distributed #multi: Distributed cooperative shared last-level caching in tiled multiprocessor system on chip (PPD, SW, AH), pp. 1–4.
DATE-2014-DinechinAPL #parallel: Time-critical computing on a single-chip massively parallel processor (BDdD, DvA, MP, GL), pp. 1–6.
DATE-2014-GaillardonAZM #design: Advanced system on a chip design based on controllable-polarity FETs (PEG, LGA, JZ, GDM), pp. 1–6.
DATE-2014-Huang14a #manycore #network #performance #predict: Leveraging on-chip networks for efficient prediction on multicore coherence (LH), pp. 1–4.
DATE-2014-KarkarDATMY #architecture #communication #hybrid: Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip (AK, ND, RAD, KT, TSTM, AY), pp. 1–4.
DATE-2014-KhdrESAH #multi #named: mDTM: Multi-objective dynamic thermal management for on-chip systems (HK, TE, MS, HA, JH), pp. 1–6.
DATE-2014-MatsutaniKFKTKBMA #3d #random: Low-latency wireless 3D NoCs via randomized shortcut chips (HM, MK, IF, TK, YT, TK, PB, RM, HA), pp. 1–6.
DATE-2014-PaternaZR #component #mobile: Ambient variation-tolerant and inter components aware thermal management for mobile system on chips (FP, JZ, TSR), pp. 1–6.
DATE-2014-PrenatPLGJDSPN #logic #power management: Magnetic memories: From DRAM replacement to ultra low power logic chips (GP, GdP, CL, OG, KJ, BD, RCS, ILP, JPN), p. 1.
DATE-2014-RamboTDAE #analysis #realtime: Failure analysis of a network-on-chip for real-time mixed-critical systems (EAR, AT, JD, LA, RE), pp. 1–4.
DATE-2014-RehmanKSH #compilation #reliability: Compiler-driven dynamic reliability management for on-chip systems under variabilities (SR, FK, MS, JH), pp. 1–4.
DATE-2014-SeitanidisPDN #architecture #named: ElastiStore: An elastic buffer architecture for Network-on-Chip routers (IS, AP, GD, CN), pp. 1–6.
DATE-2014-ShangZXY #design: Asynchronous design for new on-chip wide dynamic range power electronics (DS, XZ, FX, AY), pp. 1–6.
DATE-2014-TsaiCCC #3d #configuration management #memory management #multi: Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs (MLT, YJC, YTC, RHC), pp. 1–6.
DATE-2014-WangXWCWW #manycore #power management: Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors (XW, JX, ZW, KJC, XW, ZW), pp. 1–4.
DATE-2014-ZhuCYP: Application mapping for express channel-based networks-on-chip (DZ, LC, SY, MP), pp. 1–6.
SAC-2014-ChangTK #3d: A traffic-balanced routing scheme for heat balance in 3D networks-on-chip (WCC, HWT, CFK), pp. 1437–1442.
SAC-2014-TsaiC #3d #manycore: A thermal-throttling server in 3D multicore chips (THT, YSC), pp. 1425–1430.
HPCA-2014-AgrawalAT #energy #locality #named #process: Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules (AA, AA, JT), pp. 84–95.
HPCA-2014-AnsariMXT #energy #named #network: Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks (AA, AKM, JX, JT), pp. 440–451.
HPCA-2014-ChenZWP #named #performance: MP3: Minimizing performance penalty for power-gating of Clos network-on-chip (LC, LZ, RW, TMP), pp. 296–307.
HPCA-2014-DiTomasoKL #architecture #fault tolerance #named #power management: QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers (DD, AKK, AL), pp. 320–331.
HPCA-2014-JungK #named #resource management: Sprinkler: Maximizing resource utilization in many-chip solid state disks (MJ, MTK), pp. 524–535.
HPCA-2014-KimKMYK: Transportation-network-inspired network-on-chip (HK, GK, SM, HY, JK), pp. 332–343.
HPCA-2014-LoK #manycore: Dynamic management of TurboMode in modern multi-core chips (DL, CK), pp. 603–613.
HPCA-2014-ZhaoVZLZ0 #memory management #specification: Over-clocked SSD: Safely running beyond flash memory chip I/O clock specs (KZ, KSV, XZ, JL, NZ, TZ), pp. 536–545.
DAC-2013-CalhounC #energy #flexibility #performance #power management: Flexible on-chip power delivery for energy efficient heterogeneous systems (BHC, KC), p. 6.
DAC-2013-ChakrabortyLAP #physics: A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique (RC, CL, DA, JP), p. 10.
DAC-2013-Ghosh #memory management: Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power (SG), p. 2.
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap: Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DAC-2013-HoC #multi: Multiple chip planning for chip-interposer codesign (YKH, YWC), p. 6.
DAC-2013-KinsmanKN #generative #sequence #validation: Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation (ABK, HFK, NN), p. 6.
DAC-2013-LiP #framework #modelling: An accurate semi-analytical framework for full-chip TSV-induced stress modeling (YL, DZP), p. 8.
DAC-2013-LuYHF0 #named: RISO: relaxed network-on-chip isolation for cloud processors (HL, GY, YH, BF, XL), p. 6.
DAC-2013-MishraMD #approach #design #multi: A heterogeneous multiple network-on-chip design: an application-aware approach (AKM, OM, CRD), p. 10.
DAC-2013-SongLPL #3d #multi #optimisation: Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs (TS, CL, YP, SKL), p. 7.
DAC-2013-TurakhiaRGM #architecture #multi #named #synthesis: HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors (YT, BR, SG, DM), p. 7.
DATE-2013-AkhlaghiKAP #architecture #network #performance: An efficient network on-chip architecture based on isolating local and non-local communications (VA, MK, AAK, MP), pp. 350–353.
DATE-2013-BanaiyanMofradDG #analysis #distributed #fault tolerance #modelling: Modeling and analysis of fault-tolerant distributed memories for networks-on-chip (AB, ND, GG), pp. 1605–1608.
DATE-2013-DasKV #multi: Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems (AD, AK, BV), pp. 689–694.
DATE-2013-DimitrakopoulosGNK #multi: Switch folding: network-on-chip routers with time-multiplexed output ports (GD, NG, CN, EK), pp. 344–349.
DATE-2013-Feng #geometry #grid #power management #reduction #scalability: Large-scale flip-chip power grid reduction with geometric templates (ZF), pp. 1679–1682.
DATE-2013-FettweisHLF: Wireless interconnect for board and chip level (GF, NuH, LL, EF), pp. 958–963.
DATE-2013-LeeJS #architecture #hybrid #memory management #performance: Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs (JL, YJ, SS), pp. 1575–1578.
DATE-2013-MandalKM: Exploring topologies for source-synchronous ring-based network-on-chip (AM, SPK, RNM), pp. 1026–1031.
DATE-2013-MartinB #configuration management #integration: Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples (FM, PB), p. 169.
DATE-2013-ParkQPC #embedded #logic #self: 40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS (SP, MQ, LSP, APC), pp. 1637–1642.
DATE-2013-QianJBTMM #analysis #named #performance #using: SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model (ZQ, DCJ, PB, CYT, DM, RM), pp. 354–357.
DATE-2013-RaghunathanTGM #multi #named #process: Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors (BR, YT, SG, DM), pp. 39–44.
DATE-2013-SparsoKS #interface #network: An area-efficient network interface for a TDM-based network-on-chip (JS, EK, MS), pp. 1044–1047.
DATE-2013-TodorovMRS #approach #clustering #synthesis: A spectral clustering approach to application-specific network-on-chip synthesis (VT, DMG, HR, US), pp. 1783–1788.
DATE-2013-WangXZWYWNW #using: Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories (XW, JX, WZ, XW, YY, ZW, MN, ZW), pp. 1221–1224.
DATE-2013-WettinMPSG #approach #design #energy #manycore: Energy-efficient multicore chip design through cross-layer approach (PW, JM, PPP, BS, AG), pp. 725–730.
DATE-2013-YingHH #3d #performance: Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems (HY, TH, KH), pp. 1777–1782.
HPCA-2013-AgrawalJAT #multi #named: Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies (AA, PJ, AA, JT), pp. 400–411.
HPCA-2013-ChangHPNXK #named #network: TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network (YYC, YSCH, MP, VN, YX, CTK), pp. 390–399.
HPCA-2013-KoibuchiFMC #random: Layout-conscious random topologies for HPC off-chip interconnects (MK, IF, HM, HC), pp. 484–495.
HPCA-2013-KrishnaCKP #latency #using: Breaking the on-chip latency barrier using SMART (TK, CHOC, WCK, LSP), pp. 378–389.
HPCA-2013-LeeKH0 #power management: Skinflint DRAM system: Minimizing DRAM chip writes for low power (YL, SK, SH, JL), pp. 25–34.
CASE-2012-IchikawaA #automation: Magnetically driven micro-robot with suction mechanism for on-chip automatic (AI, FA), pp. 273–278.
DAC-2012-BathenD #distributed #hybrid #named: HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories (LADB, ND), pp. 447–452.
DAC-2012-JoubertDBTH #3d #exclamation #problem: Capacitance of TSVs in 3-D stacked chips a problem?: not for neuromorphic systems! (AJ, MD, BB, OT, RH), pp. 1264–1265.
DAC-2012-JungPL #3d #reliability: Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs (MJ, DZP, SKL), pp. 317–326.
DAC-2012-KimLCKWYL #cpu #gpu #hybrid #in memory #memory management: Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU (DK, SL, JC, DK, DHW, SY, SL), pp. 888–896.
DAC-2012-LeeC #co-evolution #design: A chip-package-board co-design methodology (HCL, YWC), pp. 1082–1087.
DAC-2012-LeeLHCCLS #design: Obstacle-avoiding free-assignment routing for flip-chip designs (PWL, HCL, YKH, YWC, CFC, IJL, CFS), pp. 1088–1093.
DAC-2012-LionelPSE #monitoring #statistics #testing: Embedding statistical tests for on-chip dynamic voltage and temperature monitoring (LV, PM, SL, EB), pp. 994–999.
DAC-2012-ParkKCDCP #prototype: Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI (SP, TK, CHOC, BKD, AC, LSP), pp. 398–405.
DAC-2012-ShafiqueZWBH #adaptation #memory management #multi #power management #video: Adaptive power management of on-chip video memory for multiview video coding (MS, BZ, FLW, SB, JH), pp. 866–875.
DAC-2012-ZhangTT #identification #using: Identification of recovered ICs using fingerprints from a light-weight on-chip sensor (XZ, NT, MT), pp. 703–708.
DAC-2012-ZhaoJDZKI #design #hybrid #multi #optimisation: A hybrid NoC design for cache coherence optimization for chip multiprocessors (HZ, OJ, WD, YZ, MTK, MJI), pp. 834–842.
DAC-2012-ZhouLCKQY #framework #monitoring: An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring (HZ, XL, CYC, EK, HQ, SCY), pp. 642–647.
DATE-2012-BartoliniSFCB #energy #performance #scalability: Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer (AB, MS, JNF, AKC, LB), pp. 181–186.
DATE-2012-BoseBDGHJNRSVW #challenge #manycore #power management: Power management of multi-core chips: Challenges and pitfalls (PB, AB, JAD, MSG, MBH, HMJ, IN, JAR, JS, AV, AJW), pp. 977–982.
DATE-2012-CondoMM #architecture: A Network-on-Chip-based turbo/LDPC decoder architecture (CC, MM, GM), pp. 1525–1530.
DATE-2012-DasSHMC #multi: Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores (AD, MS, NH, GM, ANC), pp. 479–484.
DATE-2012-DimitrakopoulosK #metaprogramming #multi #network: Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches (GD, EK), pp. 542–545.
DATE-2012-EbrahimiDLPT #algorithm #network: CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks (ME, MD, PL, JP, HT), pp. 320–325.
DATE-2012-HammamiLB #named #network #verification: NOCEVE: Network on chip emulation and verification environment (OH, XL, JMB), pp. 163–164.
DATE-2012-HsuCCLC #effectiveness #on the #pseudo: On effective flip-chip routing via pseudo single redistribution layer (HWH, MLC, HMC, HCL, SHC), pp. 1597–1602.
DATE-2012-HsuingCG: Salvaging chips with caches beyond repair (HH, BC, SKG), pp. 1263–1268.
DATE-2012-HuangBRBK #scheduling #smt: Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving (JH, JOB, AR, CB, AK), pp. 509–514.
DATE-2012-JafariJL #analysis #scheduling #worst-case: Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling (FJ, AJ, ZL), pp. 538–541.
DATE-2012-KimA #interface: On-chip source synchronous interface timing test scheme with calibration (HK, JAA), pp. 1146–1149.
DATE-2012-LiDX #process: Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations (ML, AD, LX), pp. 1591–1596.
DATE-2012-MandalKM #design #performance: A fast, source-synchronous ring-based network-on-chip design (AM, SPK, RNM), pp. 1489–1494.
DATE-2012-QianTT #configuration management #self #using: A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels (ZQ, YFT, CYT), pp. 1295–1300.
DATE-2012-RamboHS #consistency #memory management #multi #on the #verification: On ESL verification of memory consistency for system-on-chip multiprocessing (EAR, OPH, LCVdS), pp. 9–14.
DATE-2012-SunXX #design #memory management #modelling: Modeling and design exploration of FBDRAM as on-chip memory (GS, CX, YX), pp. 1507–1512.
DATE-2012-WernerOGHB #configuration management #distributed #manycore: Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems (SW, OO, DG, MH, JB), pp. 280–283.
DATE-2012-ZhengLGBYC #communication #configuration management #power management: Power-efficient calibration and reconfiguration for on-chip optical communication (YZ, PL, MG, JB, SY, KTC), pp. 1501–1506.
SAC-2012-MbarekKPA #design #modelling #power management #using: Using model driven engineering to reliably accelerate early Low Power Intent Exploration for a system-on-chip design (OM, AK, AP, MA), pp. 1580–1587.
SAC-2012-TsaiC #3d #manycore #realtime #scheduling: Thermal-aware real-time task scheduling for three-dimensional multicore chip (THT, YSC), pp. 1618–1624.
SAC-2012-ZhongGHCW #memory management: Affinity-aware DMA buffer management for reducing off-chip memory access (QZ, XG, TH, XC, KW), pp. 1588–1593.
ASPLOS-2012-DeVuystVT #execution #migration #multi: Execution migration in a heterogeneous-ISA chip multiprocessor (MD, AV, DMT), pp. 261–272.
CGO-2012-CampanoniJHRWB #automation #named #parallel #source code: HELIX: automatic parallelization of irregular programs for chip multiprocessing (SC, TMJ, GHH, VJR, GYW, DMB), pp. 84–93.
HPCA-2012-MaJW12a #adaptation #algorithm #design #performance: Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip (SM, NDEJ, ZW), pp. 467–478.
HPCA-2012-MillerPTST #named #process: Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips (TNM, XP, RT, NS, RT), pp. 27–38.
DAC-2011-AisoposCP #fault #modelling: Enabling system-level modeling of variation-induced faults in networks-on-chips (KA, CHOC, LSP), pp. 930–935.
DAC-2011-DeOrioABP #architecture #distributed #manycore #named: DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips (AD, KA, VB, LSP), pp. 912–917.
DAC-2011-JungMPL #3d #analysis #optimisation #reliability: TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC (MJ, JM, DZP, SKL), pp. 188–193.
DAC-2011-KimKY #named #network #power management: FlexiBuffer: reducing leakage power in on-chip network routers (GK, JK, SY), pp. 936–941.
DAC-2011-LiMCMS #modelling #network #performance #reliability #simulation: Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance (ZL, MM, XC, ARM, LS), pp. 735–740.
DAC-2011-LiuSCKKL #3d #analysis #optimisation: Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC (CL, TS, JC, JK, JK, SKL), pp. 783–788.
DAC-2011-PaulaNNOH #named: TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead (FMdP, AN, ZN, AO, AJH), pp. 411–416.
DAC-2011-SunLT #analysis #approximate #grid #incremental #performance #power management: Efficient incremental analysis of on-chip power grid via sparse approximation (PS, XL, MYT), pp. 676–681.
DATE-2011-Al-DujailyMXYP #concurrent #detection #network #runtime #transitive #using: Run-time deadlock detection in networks-on-chip using coupled transitive closure networks (RAD, TSTM, FX, AY, MP), pp. 497–502.
DATE-2011-AnjamNW #multi #runtime: Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor (FA, MN, SW), pp. 1358–1363.
DATE-2011-BathenD #distributed #embedded #named #power management #reliability: E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories (LADB, NDD), pp. 1141–1146.
DATE-2011-BeserraMSC #modelling #network: System-level modeling of a mixed-signal System on Chip for Wireless Sensor Networks (GSB, JEGdM, AMS, JCdC), pp. 1500–1504.
DATE-2011-BeuxTONBP #architecture #design: Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology (SLB, JT, IO, GN, GB, PGP), pp. 788–793.
DATE-2011-ChaixAZN #adaptation #concurrent #fault tolerance: A fault-tolerant deadlock-free adaptive routing for on chip interconnects (FC, DA, NEZ, MN), pp. 909–912.
DATE-2011-ChenY #design: Timing-constrained I/O buffer placement for flip-chip designs (ZWC, JTY), pp. 619–624.
DATE-2011-FunchalM #framework #modelling #named #simulation #transaction: jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip (GF, MM), pp. 1184–1187.
DATE-2011-GaoHL #debugging #multi: Eliminating data invalidation in debugging multiple-clock chips (JG, YH, XL), pp. 691–696.
DATE-2011-GhasemazarP #architecture #multi #power management: Variation aware dynamic power management for chip multiprocessor architectures (MG, MP), pp. 473–478.
DATE-2011-HuXZTS #energy #hybrid #memory management #performance #towards: Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory (JH, CJX, QZ, WCT, EHMS), pp. 746–751.
DATE-2011-IndrusiakS #performance #transaction: Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration (LSI, OMdS), pp. 1089–1094.
DATE-2011-JuanGM #3d #evaluation #multi #process #statistics: Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations (DCJ, SG, DM), pp. 383–388.
DATE-2011-KakoeeBB #communication #named #network #reliability: ReliNoC: A reliable network for priority-based on-chip communication (MRK, VB, LB), pp. 667–672.
DATE-2011-KelleyWDSRH #generative: Intermediate representations for controllers in chip generators (KK, MW, AD, PS, SR, MH), pp. 1394–1399.
DATE-2011-KozhikkottuVRD #analysis #named #performance #variability: VESPA: Variability emulation for System-on-Chip performance analysis (VJK, RV, AR, SD), pp. 2–7.
DATE-2011-NejadMG #quality: An FPGA bridge preserving traffic quality of service for on-chip network-based systems (ABN, MEM, KG), pp. 425–430.
DATE-2011-PandeCPMBMG #energy #performance #question: Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms? (PPP, FC, DP, IM, PB, RM, AG), pp. 1656–1661.
DATE-2011-ShinDLWJ: Early chip planning cockpit (JS, JAD, GL, AJW, CLJ), pp. 863–866.
DATE-2011-StranoGLFGB #architecture #scalability #self: Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture (AS, CGR, DL, MF, MEG, DB), pp. 661–666.
DATE-2011-TinoK #architecture #generative #multi: Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures (AT, GNK), pp. 485–490.
DATE-2011-WangZHLL #memory management: Flex memory: Exploiting and managing abundant off-chip optical bandwidth (YW, LZ, YH, HL, XL), pp. 968–973.
DATE-2011-XueJZZ #evaluation #performance: Floorplanning exploration and performance evaluation of a new Network-on-Chip (LX, WJ, QZ, YZ), pp. 625–630.
DATE-2011-ZhangHYG #case study #interface #reliability: Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface (WZ, JH, SY, PG), pp. 1071–1076.
DATE-2011-ZhangT #detection #hardware #named #network: RON: An on-chip ring oscillator network for hardware Trojan detection (XZ, MT), pp. 1638–1643.
SAC-2011-DaniAS #algorithm #architecture #manycore #search-based: Applying genetic algorithms to optimize the power in tiled SNUCA chip multicore architectures (AMD, BA, YNS), pp. 1090–1091.
CGO-2011-LeeT #automation #fine-grained #parallel: Automatic parallelization of fine-grained meta-functions on a chip multiprocessor (SL, JT), pp. 130–140.
CGO-2011-LiuZDK #manycore #scheduling: On-chip cache hierarchy-aware tile scheduling for multicore machines (JL, YZ, WD, MTK), pp. 161–170.
HPCA-2011-BhattacharjeeLM #multi: Shared last-level TLBs for chip multiprocessors (AB, DL, MM), pp. 62–63.
HPCA-2011-GhasemiDK #architecture #using: Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors (HRG, SCD, NSK), pp. 38–49.
HPCA-2011-HouZHWFGC #challenge #data type #performance #streaming: Efficient data streaming with on-chip accelerators: Opportunities and challenges (RH, LZ, MCH, KW, HF, YG, XC), pp. 312–320.
HPCA-2011-LeeTST #fine-grained #multi #named #thread: HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor (SL, DT, YS, JT), pp. 99–110.
HPCA-2011-NittaFA #network: Addressing system-level trimming issues in on-chip nanophotonic networks (CN, MKF, VA), pp. 122–131.
CASE-2010-MaruyamaKHTA #using: Nanomanipulation of single virus using Dielectrophoretic concentration on a microfluidic chip (HM, KK, AH, TT, FA), pp. 710–715.
DAC-2010-Ababei #design #modelling #network #optimisation #using: Network on chip design and optimization using specialized influence models (CA), pp. 625–626.
DAC-2010-CongLR #concurrent #named: ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip (JC, CL, GR), pp. 443–448.
DAC-2010-FujitaYLCAW #power management: Detachable nano-carbon chip with ultra low power (SF, SY, DL, XC, DA, HSPW), pp. 631–632.
DAC-2010-GoossensH #evolution #network: The aethereal network on chip after ten years: goals, evolution, lessons, and future (KG, AH), pp. 306–311.
DAC-2010-HuangCKT #named #network #predict: NTPT: on the end-to-end traffic prediction in the on-chip networks (YSCH, KCKC, CTK, SYT), pp. 449–452.
DAC-2010-IhrigMJ #automation #design #manycore #modelling: Automated modeling and emulation of interconnect designs for many-core chip multiprocessors (CJI, RGM, AKJ), pp. 431–436.
DAC-2010-KahngLSR #optimisation: Trace-driven optimization of networks-on-chip configurations (ABK, BL, KS, RSR), pp. 437–442.
DAC-2010-LiuZYCSZ #design: Global routing and track assignment for flip-chip designs (XL, YZ, GKY, CC, JS, XZ), pp. 90–93.
DAC-2010-MarianiBPJZS #design #multi: A correlation-based design space exploration methodology for multi-processor systems-on-chip (GM, AB, GP, JJ, VZ, CS), pp. 120–125.
DAC-2010-MicheliSMBAP #network #research: Networks on Chips: from research to products (GDM, CS, SM, LB, FA, AP), pp. 300–305.
DAC-2010-ModarressiST #architecture #configuration management #network #performance: An efficient dynamically reconfigurable on-chip network architecture (MM, HSA, AT), pp. 166–169.
DAC-2010-ShenTX #algorithm #analysis #correlation #linear #power management #statistics: A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation (RS, SXDT, JX), pp. 481–486.
DAC-2010-XieNXZLWYWL #analysis #fault: Crosstalk noise and bit error rate analysis for optical network-on-chip (YX, MN, JX, WZ, QL, XW, YY, XW, WL), pp. 657–660.
DAC-2010-YuP #clustering #manycore #memory management: Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms (CY, PP), pp. 132–137.
DAC-2010-ZengYFL #analysis #network #optimisation #power management #trade-off: Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation (ZZ, XY, ZF, PL), pp. 831–836.
DAC-2010-ZhangL #manycore #network: A multilayer nanophotonic interconnection network for on-chip many-core communications (XZ, AL), pp. 156–161.
DAC-2010-ZhaoGFH #optimisation #parallel: Parallel hierarchical cross entropy optimization for on-chip decap budgeting (XZ, YG, ZF, SH), pp. 843–848.
DATE-2010-BashirM #process #reliability #towards: Towards a chip level reliability simulator for copper/low-k backend processes (MB, LSM), pp. 279–282.
DATE-2010-ChanHBBC #analysis #named #network: PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks (JC, GH, AB, KB, LPC), pp. 691–696.
DATE-2010-ChenLJC #distributed #manycore #memory management #using: Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller (XC, ZL, AJ, SC), pp. 39–44.
DATE-2010-FacchiniMCD #3d #configuration management #memory management: An RDL-configurable 3D memory tier to replace on-chip SRAM (MF, PM, FC, WD), pp. 291–294.
DATE-2010-ForoutanTHJ #performance: An analytical method for evaluating Network-on-Chip performance (SF, YT, RH, AJ), pp. 1629–1632.
DATE-2010-GhoshS #performance #perspective: Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective (PG, AS), pp. 654–657.
DATE-2010-HePE #multi #testing: Multi-temperature testing for core-based system-on-chip (ZH, ZP, PE), pp. 208–213.
DATE-2010-JafariLJY: Optimal regulation of traffic flows in networks-on-chip (FJ, ZL, AJ, MHY), pp. 1621–1624.
DATE-2010-Jerger #named: SigNet: Network-on-chip filtering for coarse vector directories (NDEJ), pp. 1378–1383.
DATE-2010-JunYC #library #multi #network #synthesis: Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network (MJ, SY, EYC), pp. 1390–1395.
DATE-2010-KoebelC #named: SCOC3: a space computer on a chip (FK, JFC), pp. 1345–1348.
DATE-2010-LongM #bias #monitoring #network #optimisation: Optimization of the bias current network for accurate on-chip thermal monitoring (JL, SOM), pp. 1365–1368.
DATE-2010-LongMG #optimisation: Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers (JL, SOM, MG), pp. 117–122.
DATE-2010-MayWBZSHZT #agile #multi #prototype: A rapid prototyping system for error-resilient multi-processor systems-on-chip (MM, NW, AB, JZ, WS, AH, DZ, JT), pp. 375–380.
DATE-2010-PeiLL #generative #testing: An on-chip clock generation scheme for faster-than-at-speed delay testing (SP, HL, XL), pp. 1353–1356.
DATE-2010-SeiculescuMBM: A method to remove deadlocks in Networks-on-Chips with Wormhole flow control (CS, SM, LB, GDM), pp. 1625–1628.
DATE-2010-ShenHH #adaptation #configuration management: Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip (JSS, CHH, PAH), pp. 381–386.
DATE-2010-SubramanyanSSL #execution #fault tolerance #multi #performance: Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors (PS, VS, KKS, EL), pp. 1572–1577.
DATE-2010-VerbeekS #concurrent #specification: Formal specification of networks-on-chips: deadlock and evacuation (FV, JS), pp. 1701–1706.
DATE-2010-Yu: A memory- and time-efficient on-chip TCAM minimizer for IP lookup (HY), pp. 926–931.
ASPLOS-2010-BhattacharjeeM #multi: Inter-core cooperative TLB for chip multiprocessors (AB, MM), pp. 359–370.
ASPLOS-2010-KirmanM #power management #using: A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing (NK, JFM), pp. 15–28.
CC-2010-JiangZTS #analysis #distance #locality #multi #question #reuse: Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors? (YJ, EZZ, KT, XS), pp. 264–282.
HPCA-2010-LeeCC #multi #named #performance: StimulusCache: Boosting performance of chip multiprocessors with excess cache (HL, SC, BRC), pp. 1–12.
HPCA-2010-LiuJS #clustering #comprehension #how #memory management #multi #performance: Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance (FL, XJ, YS), pp. 1–12.
HPCA-2010-TangBHC #architecture #cpu #performance #using: DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance (DT, YB, WH, MC), pp. 1–12.
HPCA-2010-UdipiMB #energy #network #scalability #towards: Towards scalable, energy-efficient, bus-based on-chip networks (ANU, NM, RB), pp. 1–12.
HPCA-2010-VujicGCRMA #on the fly: DMA++: on the fly data realignment for on-chip memories (NV, MG, FC, AR, XM, EA), pp. 1–12.
HPCA-2010-XuZZY #throughput: Simple virtual channel allocation for high throughput and high frequency on-chip routers (YX, BZ, YZ, JY), pp. 1–11.
LCTES-2010-OzturkKIN #compilation #multi #reliability: Compiler directed network-on-chip reliability enhancement for chip multiprocessors (ÖÖ, MTK, MJI, SHKN), pp. 85–94.
CASE-2009-SaketiKNVK #automation #composition: Automated modular bacterial filtering system with embeddable microfluidic chips (PS, JMK, KN, LV, PJK), pp. 212–216.
DAC-2009-ChouCWCCWW #3d #manycore: No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips (SHC, CCC, CNW, YCC, TFC, CCW, JSW), pp. 587–592.
DAC-2009-DingZHCP #framework #integration #named #power management: O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration (DD, YZ, HH, RTC, DZP), pp. 264–269.
DAC-2009-FangWC #co-evolution #design: Flip-chip routing with unified area-I/O pad assignments for package-board co-design (JWF, MDFW, YWC), pp. 336–339.
DAC-2009-IsshikiLKIS #multi #simulation: Trace-driven workload simulation method for Multiprocessor System-On-Chips (TI, DL, HK, TI, KS), pp. 232–237.
DAC-2009-JangP: An SDRAM-aware router for Networks-on-Chip (WJ, DZP), pp. 800–805.
DAC-2009-KandlurK: Green data centers and hot chips (DDK, TWK), pp. 888–890.
DAC-2009-LiFMSVFPS #hybrid #named #network: Spectrum: a hybrid nanophotonic-electric on-chip network (ZL, DF, ARM, LS, MV, DF, WP, YS), pp. 575–580.
DAC-2009-VeetilSBSR #analysis #dependence #performance: Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence (VV, DS, DB, SS, SR), pp. 154–159.
DAC-2009-WangCSC #graph #power management #synthesis #using: Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (RW, NCC, BS, CKC), pp. 166–171.
DAC-2009-YingKKGGOTW #how #question: Guess, solder, measure, repeat: how do I get my mixed-signal chip right? (GY, AK, KSK, GGEG, EG, MO, ST, WW), pp. 520–521.
DAC-2009-YooYC #design #memory management #multi #performance: Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency (JhY, SY, KC), pp. 806–811.
DAC-2009-YuHZ: Variational capacitance extraction of on-chip interconnects based on continuous surface model (WY, CH, WZ), pp. 758–763.
DAC-2009-ZhangBDSJ #multi #process: Process variation characterization of chip-level multiprocessors (LZ, LSB, RPD, LS, RJ), pp. 694–697.
DATE-2009-BonnaudS #design: Cross-coupling in 65nm fully integrated EDGE System On Chip Design and cross-coupling prevention of complex 65nm SoC (PHB, GS), pp. 1045–1050.
DATE-2009-ChangBM #design #using: Customizing IP cores for system-on-chip designs using extensive external don’t-cares (KHC, VB, ILM), pp. 582–585.
DATE-2009-ChenL #design: Performance-driven dual-rail insertion for chip-level pre-fabricated design (FWC, YYL), pp. 308–311.
DATE-2009-ChouM #design: User-centric design space exploration for heterogeneous Network-on-Chip platforms (CLC, RM), pp. 15–20.
DATE-2009-ConcerIB #algorithm #named #network #novel: aEqualized: A novel routing algorithm for the Spidergon Network On Chip (NC, SI, LB), pp. 749–754.
DATE-2009-DiemerE #quality: A link arbitration scheme for quality of service in a latency-optimized network-on-chip (JD, RE), pp. 574–577.
DATE-2009-FaruqueEH #adaptation #communication #configuration management #runtime: Configurable links for runtime adaptive on-chip communication (MAAF, TE, JH), pp. 256–261.
DATE-2009-FiorinPS #monitoring #runtime: MPSoCs run-time monitoring through Networks-on-Chip (LF, GP, CS), pp. 558–561.
DATE-2009-Fujita #challenge #design #question: Nano-electronics challenge chip designers meet real nano-electronics in 2010s? (SF), pp. 431–432.
DATE-2009-GuXZ #multi #power management: A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip (HG, JX, WZ), pp. 3–8.
DATE-2009-HanssonSG #composition #named #network #predict: Aelite: A flit-synchronous Network on Chip with composable and predictable services (AH, MS, KG), pp. 250–255.
DATE-2009-HongNKO #concurrent #multi #process #thread: Process variation aware thread mapping for Chip Multiprocessors (SH, SHKN, MTK, ÖÖ), pp. 821–826.
DATE-2009-JooKH #architecture #communication: On-chip communication architecture exploration for processor-pool-based MPSoC (YPJ, SK, SH), pp. 466–471.
DATE-2009-KandemirZO #adaptation #multi: Adaptive prefetching for shared cache based chip multiprocessors (MTK, YZ, ÖÖ), pp. 773–778.
DATE-2009-KhanK09a #architecture #co-evolution #design #hardware #multi: Hardware/software co-design architecture for thermal management of chip multiprocessors (OK, SK), pp. 952–957.
DATE-2009-LiWSDS #communication #latency: Latency criticality aware on-chip communication (ZL, JW, LS, RPD, YS), pp. 1052–1057.
DATE-2009-LuCLS #co-evolution #design: Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design (CHL, HMC, CNJL, WYS), pp. 845–850.
DATE-2009-LudoviciVMRGLGB #constraints #design: Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (DL, FGV, SM, CGR, MEG, PL, GNG, DB), pp. 562–565.
DATE-2009-LuMJBWH #communication: Flow regulation for on-chip communication (ZL, MM, AJ, ACB, PvdW, TH), pp. 578–581.
DATE-2009-ModarressiSA #hybrid #network: A hybrid packet-circuit switched on-chip network based on SDM (MM, HSA, MA), pp. 566–569.
DATE-2009-PaciBB #adaptation #bias #communication #effectiveness #variability: Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels (GP, DB, LB), pp. 1404–1409.
DATE-2009-PanKK #multi #reliability: Improving yield and reliability of chip multiprocessors (AP, OK, SK), pp. 490–495.
DATE-2009-PaternaBAPDO #adaptation #multi: Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip (FP, LB, AA, FP, GD, MO), pp. 906–909.
DATE-2009-PengC #parallel #simulation: Parallel transistor level full-chip circuit simulation (HP, CKC), pp. 304–307.
DATE-2009-ReordaVMR #embedded #low cost: A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips (MSR, MV, CM, RR), pp. 352–357.
DATE-2009-SeiculescuMBM #3d #network #synthesis: SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips (CS, SM, LB, GDM), pp. 9–14.
DATE-2009-VayrynenSL #execution #fault tolerance #multi #optimisation: Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips (MV, VS, EL), pp. 484–489.
VLDB-2009-WillhalmPBPZS #in memory #named #performance #using: SIMD-Scan: Ultra Fast in-Memory Table Scan using on-Chip Vector Processing Units (TW, NP, YB, HP, AZ, JS), pp. 385–394.
HPCA-2009-Chaudhuri #locality #multi #named #policy #scalability: PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches (MC), pp. 227–238.
HPCA-2009-DasEMVD #design #evaluation: Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs (RD, SE, AKM, NV, CRD), pp. 175–186.
HPCA-2009-GrotHKM: Express Cube Topologies for on-Chip Interconnects (BG, JH, SWK, OM), pp. 163–174.
HPCA-2009-MatsutaniKAY #architecture #latency #predict: Prediction router: Yet another low latency on-chip router architecture (HM, MK, HA, TY), pp. 367–378.
HPCA-2009-MichelogiannakisBD #network: Elastic-buffer flow control for on-chip networks (GM, JDB, WJD), pp. 151–162.
HPCA-2009-WenischFAFM #memory management #metadata #streaming: Practical off-chip meta-data for temporal memory streaming (TFW, MF, AA, BF, AM), pp. 79–90.
PPoPP-2009-Dennis #how #manycore #programmable: How to build programmable multi-core chips (JBD), pp. 283–284.
PPoPP-2009-SonKKC #multi: A compiler-directed data prefetching scheme for chip multiprocessors (SWS, MTK, MK, DRC), pp. 209–218.
MBT-2009-TsiopoulosS #component #modelling #testing: Model Based Testing of a Network-on-Chip Component (LT, MS), pp. 101–116.
DAC-2008-BalkanQV #hybrid #network #parallel: An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing (AOB, GQ, UV), pp. 435–440.
DAC-2008-ChenLSK #multi: Application mapping for chip multiprocessors (GC, FL, SWS, MTK), pp. 620–625.
DAC-2008-El-MoselhyEW #algorithm #parametricity #performance #scalability #set: Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters (TAEM, IME, DW), pp. 906–911.
DAC-2008-FaruqueKH #communication #distributed #named #runtime: ADAM: run-time agent-based distributed application mapping for on-chip communication (MAAF, RK, JH), pp. 760–765.
DAC-2008-FaviC #communication: Techniques for fully integrated intra-/inter-chip optical communication (CF, EC), pp. 343–344.
DAC-2008-HerbertM #multi #variability: Characterizing chip-multiprocessor variability-tolerance (SH, DM), pp. 313–318.
DAC-2008-KwonYHMCE #approach #memory management #parallel: A practical approach of memory access parallelization to exploit multiple off-chip DDR memories (WCK, SY, SMH, BM, KMC, SKE), pp. 447–452.
DAC-2008-LaiWGLD #architecture: A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers (McL, ZW, LG, HL, KD), pp. 630–633.
DAC-2008-LinLLKWTCC: A 242mW, 10mm21080p H.264/AVC high profile encoder chip (YKL, DWL, CCL, TYK, SJW, WCT, WCC, TSC), pp. 78–83.
DAC-2008-LiZY #analysis #verification: Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification (TL, WZ, ZY), pp. 594–599.
DAC-2008-MoussaBJ #flexibility #multi #network: Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder (HM, AB, MJ), pp. 429–434.
DAC-2008-NowakCCR #design: Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration (MN, JC, CC, RR), p. 593.
DAC-2008-OgrasMM #adaptation #feedback #multi: Variation-adaptive feedback control for networks-on-chip with multiple clock domains (ÜYO, RM, DM), pp. 614–619.
DAC-2008-PuriVEWFYK #problem #question: Keeping hot chips cool: are IC thermal problems hot air? (RP, DV, DE, AJW, PDF, AY, SVK), pp. 634–635.
DAC-2008-RajaramP #design #robust #synthesis: Robust chip-level clock tree synthesis for SOC designs (AR, DZP), pp. 720–723.
DAC-2008-ZhangGT #2d #algorithm #configuration management #fault tolerance: A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip (ZZ, AG, ST), pp. 441–446.
DATE-2008-BacinschiMKG #adaptation #bias: An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs (PBB, TM, KK, MG), pp. 698–703.
DATE-2008-BadarogluDLC #using: Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment (MB, GD, FL, OC), pp. 873–878.
DATE-2008-ChouM: User-Aware Dynamic Task Allocation in Networks-on-Chip (CLC, RM), pp. 1232–1237.
DATE-2008-CornetMM #development #modelling #performance #transaction: A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip (JC, FM, LMC), pp. 9–14.
DATE-2008-DuanK #energy #performance: Energy Efficient and High Speed On-Chip Ternary Bus (CD, SPK), pp. 515–518.
DATE-2008-FarahaniFS #architecture #network #scalability #using: Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence (AFF, SMF, SS), pp. 1340–1345.
DATE-2008-FaruqueH #architecture #communication: Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures (MAAF, JH), pp. 1238–1243.
DATE-2008-HolzenspiesHKS #multi #runtime #streaming: Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC) (PKFH, JH, JK, GJMS), pp. 212–217.
DATE-2008-KwonHYMCE #communication: An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication (WCK, SMH, SY, BM, KMC, SKE), pp. 1244–1249.
DATE-2008-LiMM #concurrent #named #self #using: CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns (YL, SM, SM), pp. 885–890.
DATE-2008-LiTM #analysis #grid #named #network #power management: ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis (DL, SXDT, BM), pp. 432–437.
DATE-2008-Liu08a #correlation #performance #random #simulation: Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression (BL), pp. 527–532.
DATE-2008-MolnosHC #composition #embedded #multi: Compositional, dynamic cache management for embedded chip multiprocessors (AMM, MJMH, SDC), pp. 991–996.
DATE-2008-MoonenBBM #multi #streaming: Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip (AM, MB, RvdB, JLvM), pp. 300–305.
DATE-2008-SammanHG #architecture #parallel #pipes and filters: Multicast Parallel Pipeline Router Architecture for Network-on-Chip (FAS, TH, MG), pp. 1396–1401.
DATE-2008-ScheerSB #complexity #reduction #standard: CARbridge, Reduction of System Complexity by Standardisation of the System-Basis-Chips for Automotive Applications (PS, ES, SB), pp. 1107–1110.
DATE-2008-WangZHZT #design #multi #reliability: Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor (JW, HZ, KH, GZ, YT), pp. 792–795.
DATE-2008-YuanHX: Re-Examining the Use of Network-on-Chip as Test Access Mechanism (FY, LH, QX), pp. 808–811.
DATE-2008-ZhangYWYJX #correlation #performance #process #statistics: An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation (WZ, WY, ZW, ZY, RJ, JX), pp. 580–585.
FM-2008-KuritaCN #development #mobile #specification: Application of a Formal Specification Language in the Development of the “Mobile FeliCa” IC Chip Firmware for Embedding in Mobile Phone (TK, MC, YN), pp. 425–429.
ASPLOS-2008-BallapuramSL #behaviour #multi #semantics: Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors (CSB, AS, HHSL), pp. 60–69.
ASPLOS-2008-SrikantaiahKI #adaptation #multi #set: Adaptive set pinning: managing shared caches in chip multiprocessors (SS, MTK, MJI), pp. 135–144.
HPCA-2008-ChangCKNRST #multi: CMP network-on-chip overlaid with multi-band RF-interconnect (MFC, JC, AK, MN, GR, ES, SWT), pp. 191–202.
HPCA-2008-DasMNPNIYD #architecture #optimisation #performance: Performance and power optimization through data compression in Network-on-Chip architectures (RD, AKM, CN, DP, VN, RRI, MSY, CRD), pp. 215–225.
HPCA-2008-GratzGK: Regional congestion awareness for load balance in networks-on-chip (PG, BG, SWK), pp. 203–214.
HPCA-2008-KimGWB #analysis #performance #using: System level analysis of fast, per-core DVFS using on-chip switching regulators (WK, MSG, GYW, DMB), pp. 123–134.
CASE-2007-HolleCHHM: Characterization of Program Controlled CO2 Laser-Cut PDMS Channels for Lab-on-a-chip Applications (AWH, ShC, MH, JMH, DRM), pp. 621–627.
CASE-2007-JacksonCM: A Rationale for the use of Optical Mice Chips for Economic and Accurate Vehicle Tracking (JDJ, DWC, JM), pp. 939–944.
DAC-2007-BhojwaniM #concurrent #online #protocol #robust: A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip (PB, RNM), pp. 670–675.
DAC-2007-BogdanM #behaviour: Quantum-Like Effects in Network-on-Chip Buffers Behavior (PB, RM), pp. 266–267.
DAC-2007-Borkar #perspective: Thousand Core ChipsA Technology Perspective (SB), pp. 746–749.
DAC-2007-ChandraLRD #power management: System-on-Chip Power Management Considering Leakage Power Variations (SC, KL, AR, SD), pp. 877–882.
DAC-2007-ChanZ #modelling: Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops (HHYC, ZZ), pp. 430–435.
DAC-2007-FangHC #algorithm #design #integer #linear #programming: An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design (JWF, CHH, YWC), pp. 606–611.
DAC-2007-GhodratLR #analysis #estimation #hybrid #using: Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation (MAG, KL, AR), pp. 883–886.
DAC-2007-HeloueAN #correlation #estimation #modelling: Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation (KRH, NA, FNN), pp. 93–98.
DAC-2007-KangKR #design #power management #using: Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop (KK, KK, KR), pp. 934–939.
DAC-2007-KocKEO #embedded #memory management #multi #using: Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors (HK, MTK, EE, ÖÖ), pp. 224–229.
DAC-2007-LeungT #energy #synthesis: Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands (LFL, CYT), pp. 128–131.
DAC-2007-LiY #analysis #power management #statistics: Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage (TL, ZY), pp. 99–102.
DAC-2007-LuLJ #network: Layered Switching for Networks on Chip (ZL, ML, AJ), pp. 122–127.
DAC-2007-MarescauxC: Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT (TM, HC), pp. 116–121.
DAC-2007-Nagata #design #metric: On-Chip Measurements Complementary to Design Flow for Integrity in SoCs (MN), pp. 400–403.
DAC-2007-OgrasMCM #clustering: Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip (ÜYO, RM, PC, DM), pp. 110–115.
DAC-2007-PetlinS #functional #multi #verification: Functional Verification of SiCortex Multiprocessor System-on-a-Chip (OP, WS), pp. 906–909.
DAC-2007-ShachamBC #network #power management: The Case for Low-Power Photonic Networks on Chip (AS, KB, LPC), pp. 132–135.
DAC-2007-SolomatnikovFQSKAWHH #generative #multi: Chip Multi-Processor Generator (AS, AF, WQ, OS, KK, ZA, MW, RH, MH), pp. 262–263.
DAC-2007-YuCH #co-evolution #design: Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design (HY, CC, LH), pp. 618–621.
DAC-2007-ZhaoPRFMCSY: On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise (MZ, RP, BR, YF, TM, SC, SS, SY), pp. 162–167.
DATE-2007-BjerregaardSS #architecture #scalability: A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method (TB, MBS, JS), pp. 648–653.
DATE-2007-BrandCGB #communication: Congestion-controlled best-effort communication for networks-on-chip (JWvdB, CC, KG, TB), pp. 948–953.
DATE-2007-ChoudhuryRRM #interactive #memory management: Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory (MRC, KR, SR, KM), pp. 1072–1077.
DATE-2007-CrepaldiCGZ #design #effectiveness #top-down: An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip (MC, MRC, MG, MZ), pp. 1424–1429.
DATE-2007-EjlaliARM #energy #fault tolerance #network #performance: Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks (AE, BMAH, PMR, SGM), pp. 1647–1652.
DATE-2007-FietheMDOZ #configuration management: Reconfigurable system-on-chip data processing units for space imaging instruments (BF, HM, CD, BO, GZ), pp. 977–982.
DATE-2007-GuptaOJWB #comprehension #distributed #multi #network #using: Understanding voltage variations in chip multiprocessors using a distributed power-delivery network (MSG, JLO, RJ, GYW, DMB), pp. 624–629.
DATE-2007-HanssonCG #configuration management #multi #network: Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip (AH, MC, KG), pp. 954–959.
DATE-2007-KumarHHC #configuration management #design #interactive #multi: Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip (AK, AH, JH, HC), pp. 117–122.
DATE-2007-LaouamriA #framework #network #testing #using: Remote testing and diagnosis of System-on-Chips using network management frameworks (OL, CA), pp. 373–378.
DATE-2007-MoussaMBJ #communication #multi #network: Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding (HM, OM, AB, MJ), pp. 654–659.
DATE-2007-NjorogeCWTGKO #memory management #multi #named #transaction: ATLAS: a chip-multiprocessor with transactional memory support (NN, JC, SW, YT, DG, CK, KO), pp. 3–8.
DATE-2007-OConnorCCDHH: Heterogeneous systems on chip and systems in package (IO, BC, KC, ND, MH, JH), pp. 737–742.
DATE-2007-OgrasM #analysis #modelling #performance: Analytical router modeling for networks-on-chip performance analysis (ÜYO, RM), pp. 1096–1101.
DATE-2007-PetersenO #2d #scalability #towards: Toward a scalable test methodology for 2D-mesh Network-on-Chips (KP, JÖ), pp. 367–372.
DATE-2007-SheibanyradPG #architecture #comparison #implementation #multi #network: Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture (AS, IMP, AG), pp. 1090–1095.
DATE-2007-SirowyWLV07a #multi: Clock-frequency assignment for multiple clock domain systems-on-a-chip (SS, YW, SL, FV), pp. 397–402.
VLDB-2007-CieslewiczR #adaptation #multi: Adaptive Aggregation on Chip Multiprocessors (JC, KAR), pp. 339–350.
PLDI-2007-CoopriderR #ram: Offline compression for on-chip ram (NC, JR), pp. 363–372.
PLDI-2007-LiCKK #energy #reduction: Profile-driven energy reduction in network-on-chips (FL, GC, MTK, IK), pp. 394–404.
CIAA-2007-Watson #automaton: Automata Applications in Chip-Design Software (BWW), pp. 24–26.
HCI-AS-2007-ZhangLL #algorithm #fault #random: A Routing Algorithm for Random Error Tolerance in Network-on-Chip (LZ, HL, XL), pp. 1210–1219.
SAC-2007-ChenTL: A priority assignment strategy of processing elements over an on-chip bus (YSC, SJT, SWL), pp. 1176–1180.
SAC-2007-HungCYCS #algorithm #architecture #design #energy: An architectural co-synthesis algorithm for energy-aware network-on-chip design (WHH, YJC, CLY, YSC, APS), pp. 680–684.
SAC-2007-MoreiraMB #multi #online #resource management: Online resource management in a multiprocessor with a network-on-chip (OM, JJDM, MB), pp. 1557–1564.
GTTSE-2007-PielMD #compilation #model transformation #multi: Model Transformations for the Compilation of Multi-processor Systems-on-Chip (ÉP, PM, JLD), pp. 459–473.
HPCA-2007-AlameldeenW #interactive #multi: Interactions Between Compression and Prefetching in Chip Multiprocessors (ARA, DAW), pp. 228–239.
HPCA-2007-AnnavaramGR #variability: Implications of Device Timing Variability on Full Chip Timing (MA, EG, PR), pp. 37–45.
HPCA-2007-DybdahlS #adaptation #clustering #multi: An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors (HD, PS), pp. 2–12.
HPCA-2007-JinKY #design #network #scalability: A Domain-Specific On-Chip Network Design for Large Scale Cache Systems (YJ, EJK, KHY), pp. 318–327.
LCTES-2007-ChenLK #multi: Compiler-directed application mapping for NoC based chip multiprocessors (GC, FL, MTK), pp. 155–157.
CASE-2006-SweatNZZZ #assembly #capacity #multi: Multi-factory capacity planning in semiconductor assembly and test manufacturing with multiple-chip products (SS, SN, MTZ, ZZ, LZ), pp. 247–252.
DAC-2006-AtienzaVPPBMM #framework #multi #performance: A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip (DA, PGDV, GP, FP, LB, GDM, JMM), pp. 618–623.
DAC-2006-ChenCCCH #novel: Novel full-chip gridless routing considering double-via insertion (HYC, MFC, YWC, LC, BH), pp. 755–760.
DAC-2006-HattoriIIYKSYNYKTHAHTSMYHMYHTYIKMYITAAO #mobile #power management: Hierarchical power distribution and power management scheme for a single chip mobile processor (TH, TI, MI, EY, HK, GS, TY, KN, HY, TK, YT, MH, HA, IH, KT, YS, NM, YY, TH, YM, KY, KH, ST, SY, TI, YK, HM, TY, NI, RT, NA, TA, KO), pp. 292–295.
DAC-2006-HwangSC #array #automation #design: Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications* (WLH, FS, KC), pp. 925–930.
DAC-2006-IsseninBDD #analysis #memory management #multi #reuse: Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies (II, EB, BD, ND), pp. 49–52.
DAC-2006-KhatibPBBBKJN #analysis #architecture #design #monitoring #multi #realtime: A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration (IAK, FP, DB, LB, MB, HK, AJ, RN), pp. 125–130.
DAC-2006-LeeOMC #design #multi #prototype: Design space exploration and prototyping for on-chip multimedia applications (HGL, ÜYO, RM, NC), pp. 137–142.
DAC-2006-LeungT #performance #scheduling: Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems (LFL, CYT), pp. 833–838.
DAC-2006-LiLP #analysis #power management #statistics: Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions (XL, JL, LTP), pp. 103–108.
DAC-2006-LiZJ #concurrent #named #network #proximity: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip (ML, QAZ, WBJ), pp. 849–852.
DAC-2006-MuraliABM #fault tolerance #multi #network: A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip (SM, DA, LB, GDM), pp. 845–848.
DAC-2006-OgrasM #predict: Prediction-based flow control for network-on-chip traffic (ÜYO, RM), pp. 839–844.
DAC-2006-PandeyG #communication #constraints #scalability #statistics #synthesis: Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint (SP, MG), pp. 663–668.
DAC-2006-ShethSM #design: The importance of adopting a package-aware chip design flow (KS, ES, JM), pp. 853–856.
DAC-2006-ZhaoPSYF #algorithm #linear #megamodelling #performance #programming #using: A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming (MZ, RP, SS, SY, YF), pp. 217–222.
DATE-2006-AbbasIA #detection: On-chip 8GHz non-periodic high-swing noise detector (MA, MI, KA), pp. 670–671.
DATE-2006-BertozziABP #migration #multi: Supporting task migration in multi-processor systems-on-chip: a feasibility study (SB, AA, DB, AP), pp. 15–20.
DATE-2006-GuzWBCGK #capacity #design #performance: Efficient link capacity and QoS design for network-on-chip (ZG, IW, EB, IC, RG, AK), pp. 9–14.
DATE-2006-LaMeresK #encoding #induction: Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission (BJL, SPK), pp. 522–527.
DATE-2006-LeeKKCY #adaptation #using: A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes (SJL, KK, HK, NC, HJY), pp. 79–80.
DATE-2006-LiuI #optimisation #scheduling #using: Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking (CL, VI), pp. 652–657.
DATE-2006-LiuLP #scheduling: Reuse-based test access and integrated test scheduling for network-on-chip (CL, ZL, DKP), pp. 303–308.
DATE-2006-MolnosHCE #composition #multi #performance: Compositional, efficient caches for a chip multi-processor (AMM, MJMH, SDC, JTJvE), pp. 345–350.
DATE-2006-MuraliCRGM #multi #network: A methodology for mapping multiple use-cases onto networks on chips (SM, MC, AR, KG, GDM), pp. 118–123.
DATE-2006-OgrasMLC #architecture #communication #optimisation: Communication architecture optimization: making the shortest path shorter in regular networks-on-chip (ÜYO, RM, HGL, NC), pp. 712–717.
DATE-2006-PionteckAK #configuration management: A dynamically reconfigurable packet-switched network-on-chip (TP, CA, RK), pp. 136–137.
DATE-2006-RossiSM #analysis: Analysis of the impact of bus implemented EDCs on on-chip SSN (DR, CS, CM), pp. 59–64.
DATE-2006-RuggieroGBPM #framework #multi #scheduling: Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip (MR, AG, DB, FP, MM), pp. 3–8.
DATE-2006-SehgalGMC #design #framework: Hierarchy-aware and area-efficient test infrastructure design for core-based system chips (AS, SKG, EJM, KC), pp. 285–290.
DATE-2006-SekarLRD #adaptation #configuration management: Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms (KS, KL, AR, SD), pp. 728–733.
DATE-2006-SrinivasanC #architecture #complexity #design #heuristic: A low complexity heuristic for design of custom network-on-chip architectures (KS, KSC), pp. 130–135.
DATE-2006-SundaresanM #energy #optimisation: Value-based bit ordering for energy optimization of on-chip global signal buses (KS, NRM), pp. 624–625.
DATE-2006-WangM #algorithm #analysis #multi: A logarithmic full-chip thermal analysis algorithm based on multi-layer Green’s function (BW, PM), pp. 39–44.
DATE-2006-WangXVI #analysis #optimisation: On-chip bus thermal analysis and optimization (FW, YX, NV, MJI), pp. 850–855.
DATE-2006-WildHO #architecture #evaluation #performance #simulation #transaction #using: Performance evaluation for system-on-chip architectures using trace-based transaction level simulation (TW, AH, RO), pp. 248–253.
DATE-2006-YangGZSD #adaptation #analysis #design #synthesis: Adaptive chip-package thermal analysis for synthesis and design (YY, Z(G, CZ, LS, RPD), pp. 844–849.
DATE-DF-2006-AkselrodAA #architecture #debugging #framework #independence #multi #security: Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs (DA, AA, YA), pp. 30–35.
DATE-DF-2006-BononiC #2d #analysis #architecture #network #simulation: Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh (LB, NC), pp. 154–159.
DATE-DF-2006-CampobelloCCM #network: GALS networks on chip: a new solution for asynchronous delay-insensitive links (GC, MC, CC, DM), pp. 160–165.
DATE-DF-2006-SteenhofDNGL #architecture #network: Networks on chips for high-end consumer-electronics TV system architectures (FS, HD, BN, KG, RPL), pp. 148–153.
DATE-DF-2006-YehHCWC #design: An 830mW, 586kbps 1024-bit RSA chip design (CY, EFH, KWC, JSW, NJC), pp. 24–29.
MoDELS-2006-SchattkowskyHE #design #process #synthesis #uml #using: Using UML Activities for System-on-Chip Design and Synthesis (TS, JHH, GE), pp. 737–752.
MoDELS-2006-SchattkowskyHE #design #process #synthesis #uml #using: Using UML Activities for System-on-Chip Design and Synthesis (TS, JHH, GE), pp. 737–752.
POPL-2006-ChenLK #network: Compiler-directed channel allocation for saving power in on-chip networks (GC, FL, MTK), pp. 194–205.
SAC-2006-OrshanskyWCX #analysis #robust #statistics: Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips (MO, WSW, MC, GX), pp. 1645–1649.
ASPLOS-2006-KgilDSBDMRF #3d #energy #multi #named #performance #using: PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor (TK, SD, AGS, NLB, RGD, TNM, SKR, KF), pp. 117–128.
ASPLOS-2006-MysoreASLBS #3d: Introspective 3D chips (SM, BA, NS, SCL, KB, TS), pp. 264–273.
HPCA-2006-Emma #capacity #evolution #industrial: Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth (PGE), p. 201.
HPCA-2006-LiM #adaptation #parallel: Dynamic power-performance adaptation of parallel computation on chip multiprocessors (JL, JFM), pp. 77–87.
HPCA-2006-PenryFHWSAC #parallel #simulation: Exploiting parallelism and structure to accelerate the simulation of chip multi-processors (DAP, DF, DH, RW, GS, DIA, DC), pp. 29–40.
HPCA-2006-Stenstrom #multi: Chip-multiprocessing and beyond (PS), p. 109.
DAC-2005-AhmadM #logic: TCAM enabled on-chip logic minimization (SA, RNM), pp. 678–683.
DAC-2005-ChangS #analysis #correlation #power management #process: Full-chip analysis of leakage power under process variations, including spatial correlations (HC, SSS), pp. 523–528.
DAC-2005-HoCCC #architecture #multi: Multilevel full-chip routing for the X-based architecture (TYH, CFC, YWC, SJC), pp. 597–602.
DAC-2005-KimPTVD #adaptation #latency: A low latency router supporting adaptivity for on-chip interconnects (JK, DP, TT, NV, CRD), pp. 559–564.
DAC-2005-LinH #performance #reduction: Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction (YL, LH), pp. 720–725.
DAC-2005-LiQTWCH #approach #clustering #performance: Partitioning-based approach to fast on-chip decap budgeting and minimization (HL, ZQ, SXDT, LW, YC, XH), pp. 170–175.
DAC-2005-PuriSB: Keeping hot chips cool (RP, LS, SB), pp. 285–288.
DAC-2005-SekarLRD #architecture #communication #configuration management #named: FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology (KS, KL, AR, SD), pp. 571–574.
DAC-2005-YangWK #architecture: Secure scan: a design-for-test architecture for crypto chips (BY, KW, RK), pp. 135–140.
DATE-2005-AmoryLMM #architecture #multi #reduction #reuse: Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture (AMA, ML, FGM, EIM), pp. 62–63.
DATE-2005-BeckBKPLP #design #generative #implementation #logic #quality: Logic Design for On-Chip Test Clock Generation — Implementation Details and Impact on Delay Test Quality (MB, OB, MK, FP, XL, RP), pp. 56–61.
DATE-2005-BjerregaardS #architecture: A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip (TB, JS), pp. 1226–1231.
DATE-2005-Campagnolo #detection #generative: eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection (RC), pp. 1338–1339.
DATE-2005-CheungLC #configuration management: Reconfigurable Elliptic Curve Cryptosystems on a Chip (RCCC, WL, PYKC), pp. 24–29.
DATE-2005-ChureauSA #functional #prototype #uml: The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application (AC, YS, EMA), pp. 698–703.
DATE-2005-GenkoAMMHC #framework: A Complete Network-On-Chip Emulation Framework (NG, DA, GDM, JMM, RH, FC), pp. 246–251.
DATE-2005-GoelM #design #framework #multi #testing: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips (SKG, EJM), pp. 44–49.
DATE-2005-GoossensDGPRR #design #network #performance #verification: A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification (KG, JD, OPG, SGP, AR, ER), pp. 1182–1187.
DATE-2005-HungBK #multi #programmable #symmetry: Symmetric Multiprocessing on Programmable Chips Made Easy (AH, WDB, AAK), pp. 240–245.
DATE-2005-KallakuriDF #communication: Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip (SK, AD, EAF), pp. 826–827.
DATE-2005-KaulSBMA #design #fault: DVS for On-Chip Bus Designs Based on Timing Error Correction (HK, DS, DB, TNM, TMA), pp. 80–85.
DATE-2005-LaMeresK #encoding #induction: Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission (BJL, SPK), pp. 1318–1323.
DATE-2005-LinkV #configuration management #runtime: Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip (GML, NV), pp. 648–649.
DATE-2005-MahadevanASOSM #generative #network #performance #simulation: A Network Traffic Generator Model for Fast Network-on-Chip Simulation (SM, FA, MS, RGO, JS, JM), pp. 780–785.
DATE-2005-Martin #component #design #transaction: Design of a Virtual Component Neutral Network-on-Chip Transaction Layer (PM), pp. 336–337.
DATE-2005-MellorWM #uml #why: Why Systems-on-Chip Needs More UML like a Hole in the Head (SJM, JRW, CM), pp. 834–835.
DATE-2005-NoguchiN #monitoring #multi: On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits (KN, MN), pp. 146–151.
DATE-2005-NolletMAM #configuration management #hardware #resource management #runtime: Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles (VN, TM, PA, JYM), pp. 234–239.
DATE-2005-SrinivasanLV #architecture #clustering: Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures (SS, LL, NV), pp. 218–223.
DATE-2005-StergiouACRBM #abstract syntax tree #design #library #network #pipes and filters #synthesis: ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips (SS, FA, SC, LR, DB, GDM), pp. 1188–1193.
DATE-2005-StuijkBMG #data type #multi #predict #scalability: Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip (SS, TB, BM, MG), pp. 254–255.
DATE-2005-TsaiVXI #network: Leakage-Aware Interconnect for On-Chip Network (YFT, NV, YX, MJI), pp. 230–231.
DATE-2005-VillaSVMP #framework #integration #memory management #multi #performance: Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip (OV, PS, IV, MM, GP), pp. 804–805.
DATE-2005-WangPM #energy #network: A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks (HW, LSP, SM), pp. 1238–1243.
DATE-2005-WeberCSW #network: A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips (WDW, JC, IS, DW), pp. 1232–1237.
DATE-2005-Wolf #multi: Multimedia Applications of Multiprocessor Systems-on-Chips (WW), pp. 86–89.
DATE-2005-YangCK #algorithm #approximate #energy #multi #scheduling: An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor (CYY, JJC, TWK), pp. 468–473.
ICDAR-2005-ZaidiRM #design #hardware #online #recognition #using: Hardware Design of On-Line Jawi Character Recognition Chip using Discrete Wavelet Transform (RZ, SR, MY), pp. 91–95.
VLDB-2005-ColohanASM #parallel #transaction: Optimistic Intra-Transaction Parallelism on Chip Multiprocessors (CBC, AA, JGS, TCM), pp. 73–84.
SIGAda-2005-NaeserAF #monitoring #named: SafetyChip: a time monitoring and policing device (GN, LA, JF), pp. 63–68.
HPCA-2005-ChandraGKS #architecture #multi #predict #thread: Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture (DC, FG, SK, YS), pp. 340–351.
HPCA-2005-SpracklenA #challenge #multi #thread: Chip Multithreading: Opportunities and Challenges (LS, SGA), pp. 248–252.
HPCA-2005-SpracklenCA #effectiveness #multi: Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications (LS, YC, SGA), pp. 225–236.
DAC-2004-BriskKS #configuration management #design #set #synthesis: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs (PB, AK, MS), pp. 395–400.
DAC-2004-ChoiSP #scalability: Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding (KC, RS, MP), pp. 544–549.
DAC-2004-HuM #named: DyAD: smart routing for networks-on-chip (JH, RM), pp. 260–263.
DAC-2004-Kandemir #multi #named #scheduling: LODS: locality-oriented dynamic scheduling for on-chip multiprocessors (MTK), pp. 125–128.
DAC-2004-Micheli #communication #reliability: Reliable communication in systems on chips (GDM), p. 77.
DAC-2004-MoB #design: A timing-driven module-based chip design flow (FM, RKB), pp. 67–70.
DAC-2004-NakamuraHKYY #c #c++ #communication #hardware #performance #using: A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication (YN, KH, IK, KY, TY), pp. 299–304.
DAC-2004-NolletMVMV #network: Operating-system controlled network on chip (VN, TM, DV, JYM, SV), pp. 256–259.
DAC-2004-SridharaS #framework #network: Coding for system-on-chip networks: a unified framework (SRS, NRS), pp. 103–106.
DAC-2004-TanjiA #analysis #distributed: Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects (YT, HA), pp. 810–813.
DAC-2004-Wolf #future of #multi: The future of multiprocessor systems-on-chips (WW), pp. 681–685.
DAC-2004-ZhangHC #analysis #pipes and filters #statistics: Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining (LZ, YH, CCPC), pp. 904–907.
DATE-DF-2004-AitkenM #dependence #design: From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions (RCA, FM), p. 2.
DATE-DF-2004-BainbridgePF #design #self #using: The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip (WJB, LAP, SBF), pp. 274–279.
DATE-DF-2004-BonaZZ #industrial #modelling #simulation: System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip (AB, VZ, RZ), pp. 318–323.
DATE-DF-2004-CoppolaCGMP #framework #modelling #named #simulation: OCCN: A Network-On-Chip Modeling and Simulation Framework (MC, SC, MDG, GM, FP), pp. 174–179.
DATE-DF-2004-ElfadelDKRS: A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses (IME, AD, GVK, BR, HS), pp. 144–149.
DATE-DF-2004-GoelCMNO #design #framework: Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip (SKG, KC, EJM, TN, SO), pp. 108–113.
DATE-DF-2004-LoukusaPRRV #design #perspective: Systems on Chips Design: System Manufacturer Point of View (VL, HP, AR, TR, OV), pp. 3–4.
DATE-DF-2004-MenichelliOBDB #architecture #design #multi #power management: A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design (FM, MO, LB, MD, LB), pp. 312–317.
DATE-DF-2004-SchmittR #design #low cost #prototype #using #verification: Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments (SS, WR), pp. 96–101.
DATE-DF-2004-ZeferinoKS #named: RASoC: A Router Soft-Core for Networks-on-Chip (CAZ, MEK, AAS), pp. 198–205.
DATE-v1-2004-BriereCMMOG #behaviour #design #modelling #tool support: Design and Behavioral Modeling Tools for Optical Network-on-Chip (MB, LC, TM, FM, IO, FG), pp. 738–739.
DATE-v1-2004-ChoiSP #energy #fine-grained #performance #precise #scalability #trade-off: Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times (KC, RS, MP), pp. 4–9.
DATE-v1-2004-HeathBH #named #nondeterminism: Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s (MWH, WPB, IGH), pp. 410–415.
DATE-v1-2004-HuM #architecture #communication #constraints #energy #realtime #scheduling: Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints (JH, RM), pp. 234–239.
DATE-v1-2004-KretzschmarNM #power management #why: Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work (CK, AKN, DM), pp. 512–517.
DATE-v1-2004-MurgaiRMHT #analysis #modelling: Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis (RM, SMR, TM, TH, MBT), pp. 610–615.
DATE-v1-2004-RolindezMPB #generative #implementation: A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns (LR, SM, GP, AB), pp. 706–707.
DATE-v1-2004-SiebenbornBR #analysis #communication #design: Communication Analysis for System-On-Chip Design (AS, OB, WR), pp. 648–655.
DATE-v1-2004-ThepayasuwanD #architecture #layout #synthesis: Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (NT, AD), pp. 108–113.
DATE-v1-2004-WinkelmannTSF #low cost #verification: Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor (KW, HJT, DS, GF), pp. 162–167.
DATE-v2-2004-AbasRK #design #metric: Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit (MAA, GR, DJK), pp. 804–809.
DATE-v2-2004-BanerjeeVC #architecture #performance: A Power and Performance Model for Network-on-Chip Architectures (NB, PV, KSC), pp. 1250–1255.
DATE-v2-2004-DengW #algorithm: Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus (LD, MDFW), pp. 1104–1109.
DATE-v2-2004-DuanK: Exploiting Crosstalk to Speed up On-Chip Buse (CD, SPK), pp. 778–783.
DATE-v2-2004-GoudarziHM #implementation #modelling #morphism #object-oriented #polymorphism: Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models (MG, SH, AM), pp. 1380–1381.
DATE-v2-2004-JalabertMBM #network: ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip (AJ, SM, LB, GDM), pp. 884–889.
DATE-v2-2004-KadayifKK #energy #multi: Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors (IK, MTK, IK), pp. 1158–1163.
DATE-v2-2004-LaouamriA #network #protocol #testing #using: Enhancing Testability of System on Chips Using Network Management Protocols (OL, CA), pp. 1370–1371.
DATE-v2-2004-LinZ #fixpoint: Wire Retiming for System-on-Chip by Fixpoint Computation (CL, HZ), pp. 1092–1097.
DATE-v2-2004-LoghiABBZ #communication: Analyzing On-Chip Communication in a MPSoC Environment (ML, FA, DB, LB, RZ), pp. 752–757.
DATE-v2-2004-MillbergNTJ #network #using: Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip (MM, EN, RT, AJ), pp. 890–895.
DATE-v2-2004-PestanaRRGG #approach #network #trade-off: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach (SGP, ER, AR, KGWG, OPG), pp. 764–769.
DATE-v2-2004-RadulescuDGRW #abstraction #flexibility #interface #network #performance: An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration (AR, JD, KGWG, ER, PW), pp. 878–883.
DATE-v2-2004-TehranipourNC #flexibility #testing: Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression (MHT, MN, KC), pp. 1284–1289.
DATE-v2-2004-WieferinkKLAMBN #communication #framework #multi: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform (AW, TK, RL, GA, HM, GB, AN), pp. 1256–1263.
DATE-v2-2004-XiongH #multi: Full-Chip Multilevel Routing for Power and Signal Integrity (JX, LH), pp. 1116–1123.
DATE-v2-2004-XuWHCL #case study #design #embedded #video: A Case Study in Networks-on-Chip Design for Embedded Video (JX, WW, JH, STC, TL), pp. 770–777.
DATE-2005-MelloMCM04 #multi #named #network: MultiNoC: A Multiprocessing System Enabled by a Network on Chip (AM, LM, NC, FGM), pp. 234–239.
SAC-2004-MengC #analysis #scalability: Bio-sequence analysis with cradle’s 3SoC^TM software scalable system on chip (XM, VC), pp. 202–206.
SAC-2004-MortonL #design #hardware #kernel: A hardware/software kernel for system on chip designs (AM, WML), pp. 869–875.
HPCA-2004-Michaud #capacity #execution #manycore #migration: Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration (PM), pp. 186–197.
DAC-2003-AgarwalSB #effectiveness: An effective capacitance based driver output model for on-chip RLC interconnects (KA, DS, DB), pp. 376–381.
DAC-2003-AmmerSKKR #energy: A low-energy chip-set for wireless intercom (MJA, MS, TCK, MK, JMR), pp. 916–919.
DAC-2003-BashirullahLC #adaptation #design #power management: Low-power design methodology for an on-chip bus with adaptive bandwidth capability (RB, WL, RKCI), pp. 628–633.
DAC-2003-BergamaschiJ #analysis: State-based power analysis for systems-on-chip (RAB, YJ), pp. 638–641.
DAC-2003-GorenZGWBALSTGPJSSDH #design #modelling: On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices (DG, MZ, RG, IAW, AB, AA, BL, AS, YT, RAG, JP, DLJ, SES, RS, CED, DLH), pp. 724–727.
DAC-2003-LyseckyV #logic: On-chip logic minimization (RLL, FV), pp. 334–337.
DAC-2003-MagarshackP: System-on-chip beyond the nanometer wall (PM, PGP), pp. 419–424.
DAC-2003-Matsuzawa #collaboration #communication #how #optimisation #performance: How to make efficient communication, collaboration, and optimization from system to chip (AM), pp. 417–418.
DAC-2003-RaghunathanSG #bibliography #communication #energy #performance: A survey of techniques for energy efficient on-chip communication (VR, MBS, RKG), pp. 900–905.
DAC-2003-Visweswariah: Death, taxes and failing chips (CV), pp. 343–347.
DAC-2003-WangM #multi #network #optimisation #power management #using: On-chip power supply network optimization using multigrid-based technique (KW, MMS), pp. 113–118.
DATE-2003-AdriahantenainaCGMZ #named #scalability: SPIN: A Scalable, Packet Switched, On-Chip Micro-Network (AA, HC, AG, LM, CAZ), pp. 20070–20073.
DATE-2003-BeckerTVB #architecture #configuration management #industrial #integration: An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration (JB, AT, MV, VB), pp. 11120–11121.
DATE-2003-BurbidgeTR #automation #embedded #monitoring: Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops (MJB, JT, AR), pp. 10496–10503.
DATE-2003-ChoLYCZ #analysis #communication #design #scheduling: Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design (YC, GL, SY, KC, NEZ), pp. 20132–20137.
DATE-2003-DumitrasM #communication #probability: On-Chip Stochastic Communication (TD, RM), pp. 10790–10795.
DATE-2003-IwasakiNNNYONTOIE #multi #scalability: Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level (HI, JN, KN, KN, TY, MO, YN, YT, TO, MI, ME), pp. 20002–20007.
DATE-2003-KandemirZK #parallel #runtime: Runtime Code Parallelization for On-Chip Multiprocessors (MTK, WZ, MK), pp. 10510–10515.
DATE-2003-LiuC #approach #fault #identification: A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis (CL, KC), pp. 10230–10237.
DATE-2003-LykakisMVNPSKPR #performance #protocol: Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip (GL, NM, KV, NAN, SP, GS, GEK, DNP, DIR), pp. 20014–20019.
DATE-2003-MamidipakaD #architecture #embedded #memory management #power management #stack: On-chip Stack Based Memory Organization for Low Power Embedded Architectures (MM, NDD), pp. 11082–11089.
DATE-2003-MignoletNCVVL #configuration management #design #framework: Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip (JYM, VN, PC, DV, SV, RL), pp. 10986–10993.
DATE-2003-NilssonMOJ #network #proximity: Load Distribution with the Proximity Congestion Awareness in a Network on Chip (EN, MM, JÖ, AJ), pp. 11126–11127.
DATE-2003-PanBKK #analysis #architecture #design #programmable: Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver (CP, NB, AHK, AK), pp. 10468–10475.
DATE-2003-PetrotG #api #implementation #lightweight #multi #thread: Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect (FP, PG), pp. 20051–20056.
DATE-2003-RijpkemaGRDMWW #design #network: Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip (ER, KGWG, AR, JD, JLvM, PW, EW), pp. 10350–10355.
DATE-2003-RoychoudhuryMK #debugging #protocol #using: Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol (AR, TM, SRK), pp. 10828–10833.
DATE-2003-Sanchez-ElezFADBH #architecture #configuration management #data transformation #energy #memory management #multi: Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures (MSE, MF, MLA, HD, NB, RH), pp. 10036–10043.
DATE-2003-SayintaCPAD #abstraction #case study #using #verification: A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification (AS, GC, MP, AA, WD), pp. 20095–20100.
DATE-2003-StolbergBFMFMKKP #architecture #manycore #named: HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications (HJS, MB, LF, SM, SF, XM, MBK, HK, PP), pp. 20008–20013.
DATE-2003-YeBM #analysis #communication: Packetized On-Chip Interconnect Communication Analysis for MPSoC (TTY, LB, GDM), pp. 10344–10349.
VLDB-2003-BouganimNPW #data access #encryption: Chip-Secured Data Access: Reconciling Access Rights with Data Encryption (LB, FDN, PP, LW), pp. 1133–1136.
HPCA-2003-Bhandarkar #enterprise: Billion Transistor Chips in Mainstream Enterprise Platforms of the Future (DB), p. 3.
HPCA-2003-HoP #communication #design #performance: A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns (WHH, TMP), pp. 377–388.
HPCA-2003-TaylorLAA #architecture #network: Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture (MBT, WL, SPA, AA), pp. 341–353.
DAC-2002-AmickGL #concept #interface #megamodelling: Macro-modeling concepts for the chip electrical interface (BWA, CRG, DL), pp. 391–394.
DAC-2002-KadayifKS #approach #integer #linear #multi #programming: An integer linear programming based approach for parallelizing applications in On-chip multiprocessors (IK, MTK, US), pp. 703–708.
DAC-2002-LinBP #2d #modelling #on the: On the efficacy of simplified 2D on-chip inductance models (TL, MWB, LTP), pp. 757–762.
DAC-2002-LyseckyCV #memory management #performance #profiling: A fast on-chip profiler memory (RLL, SC, FV), pp. 28–33.
DAC-2002-Pogge #challenge #effectiveness: The next chip challenge: effective methods for viable mixed technology SoCs (HBP), pp. 84–87.
DAC-2002-VaratkarM #analysis #design #multi #network: Traffic analysis for on-chip networks design of multimedia applications (GV, RM), pp. 795–800.
DAC-2002-WhelihanS #memory management #network #optimisation: Memory optimization in single chip network switch fabrics (DW, HS), pp. 530–535.
DATE-2002-BertozziBM #encoding #fault #power management: Low Power Error Resilient Encoding for On-Chip Data Buses (DB, LB, GDM), pp. 102–109.
DATE-2002-CarmonaJDER #design #programmable: Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip (RCG, FJG, RDC, SEM, ÁRV), pp. 362–366.
DATE-2002-FavalliD #approach #design #generative #pseudo #random testing: An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators (MF, MD), p. 1122.
DATE-2002-GonciariAN #testing: Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression (PTG, BMAH, NN), pp. 604–611.
DATE-2002-GorenZGGLASW #approach #design: An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach (DG, MZ, TCG, RG, BL, AA, AS, IAW), pp. 804–811.
DATE-2002-LiHCSWCCHL #design: A Hierarchical Test Scheme for System-On-Chip Designs (JFL, HJH, JBC, CPS, CWW, CC, SIC, CYH, HPL), pp. 486–490.
DATE-2002-LinBP #3d #modelling #question: On-Chip Inductance Models: 3D or Not 3D? (TL, MWB, LTP), p. 1112.
DATE-2002-MicheliB #design #network #paradigm: Networks on Chip: A New Paradigm for Systems on Chip Design (GDM, LB), pp. 418–419.
DATE-2002-RigaudFRQ #communication #design #modelling: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems (JBR, LF, MR, JQ), p. 1090.
DATE-2002-SimunicB #network #power management: Managing Power Consumption in Networks on Chip (TS, SPB), pp. 110–116.
DATE-2002-WilliamsHA #communication #parallel: Communication Mechanisms for Parallel DSP Systems on a Chip (JW, NH, BDA), pp. 420–422.
DATE-2002-YmeriNMRSV #approach #parametricity #performance: Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate (HY, BN, KM, DDR, MS, SV), p. 1113.
VLDB-2002-BouganimP #data access: Chip-Secured Data Access: Confidential Data on Untrusted Servers (LB, PP), pp. 131–142.
ASPLOS-2002-KimBK #adaptation: An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (CK, DB, SWK), pp. 211–222.
HPCA-2002-BorchTME: Loose Loops Sink Chips (EB, ET, SM, JSE), pp. 299–310.
LCTES-SCOPES-2002-Magarshack #development #embedded #industrial #perspective: Systems-on-chip needs for embedded software development: an industrial perspective (PM), p. 1.
DAC-2001-BanerjeeM #analysis #distributed #novel #optimisation #performance #using: Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects (KB, AM), pp. 798–803.
DAC-2001-BeattieP01a #modelling: Modeling Magnetic Coupling for On-Chip Interconnect (MWB, LTP), pp. 335–340.
DAC-2001-BeniniMMMP #architecture #embedded #layout #memory management #synthesis: From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (LB, LM, AM, EM, MP), pp. 784–789.
DAC-2001-ChandraC #power management #testing: Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip (AC, KC), pp. 166–169.
DAC-2001-ChenBD #embedded #fault #testing #using: Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores (LC, XB, SD), pp. 317–320.
DAC-2001-DallyT #network: Route Packets, Not Wires: On-Chip Interconnection Networks (WJD, BT), pp. 684–689.
DAC-2001-DanielSW #analysis #performance #using: Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and Off-Chip Interconnect (LD, ALSV, JW), pp. 563–566.
DAC-2001-KarimNDR #architecture #communication #network: On-Chip Communication Architecture for OC-768 Network Processors (FK, AN, SD, RRR), pp. 678–683.
DAC-2001-LahiriRL #architecture #communication #design #named: LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs (KL, AR, GL), pp. 15–20.
DAC-2001-LaiC #testing: Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip (WCL, KTC), pp. 59–64.
DAC-2001-LuCYP #metric #modelling: Min/max On-Chip Inductance Models and Delay Metrics (YCL, MC, TY, LTP), pp. 341–346.
DAC-2001-LyonnardYBJ #architecture #automation #generative #multi: Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip (DL, SY, AB, AAJ), pp. 518–523.
DAC-2001-MeguerdichianDK #design #multi: Latency-Driven Design of Multi-Purpose Systems-On-Chip (SM, MD, DK), pp. 27–30.
DAC-2001-SgroiSMKMRS #design: Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design (MS, MS, AM, KK, SM, JMR, ALSV), pp. 667–672.
DAC-2001-WangKMR #hardware #set: Hardware/Software Instruction Set Configurability for System-on-Chip Processors (AW, EK, DEM, CR), pp. 184–188.
DAC-2001-Zeijl #challenge: One-chip Bluetooth ASIC Challenges (PTMvZ), p. 262.
DATE-2001-AkgulM #hardware: System-on-a-chip processor synchronization support in hardware (BSA, VJMI), pp. 633–641.
DATE-2001-ChandraC #performance #testing #using: Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding (AC, KC), pp. 145–149.
DATE-2001-Chen #grid #on the #power management: On the impact of on-chip inductance on signal nets under the influence of power grid noise (TC), pp. 451–459.
DATE-2001-HuangM #configuration management #design #network #using: Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks (ZH, SM), p. 735.
DATE-2001-LarssonP #framework: An integrated system-on-chip test framework (EL, ZP), pp. 138–144.
DATE-2001-Mandapati #implementation: Implementation of the ATI flipper chip (AM), pp. 697–698.
DATE-2001-PiguetRO #power management: Low-power systems on chips (SOCs) (CP, MR, TJFO), p. 488.
DATE-2001-ZengABA #identification: Full chip false timing path identification: applications to the PowerPCTM microprocessors (JZ, MSA, JB, JAA), pp. 514–519.
DAC-2000-BaiDR #self: Self-test methodology for at-speed test of crosstalk in chip interconnects (XB, SD, JR), pp. 619–624.
DAC-2000-BergamaschiL #design #using: Designing systems-on-chip using cores (RAB, WRL), pp. 420–425.
DAC-2000-Chakrabarty #architecture #constraints #design: Design of system-on-a-chip test access architectures under place-and-route and power constraints (KC), pp. 432–437.
DAC-2000-DallyC #design: The role of custom design in ASIC Chips (WJD, AC), pp. 643–647.
DAC-2000-DesmetVM #generative #operating system: Operating system based software generation for systems-on-chip (DD, DV, HDM), pp. 396–401.
DAC-2000-GalaZPYWB #analysis #modelling: On-chip inductance modeling and analysis (KG, VZ, RP, BY, JW, DB), pp. 63–68.
DAC-2000-KashyapK: A realizable driving point model for on-chip interconnect with inductance (CVK, BK), pp. 190–195.
DAC-2000-LahiriRLD #architecture #communication #design: Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips (KL, AR, GL, SD), pp. 513–518.
DAC-2000-ZorianM #design #how #question: System chip test: how will it impact your design? (YZ, EJM), pp. 136–141.
DATE-2000-BenabdenebiMM #configuration management #named #scalability: CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip (MB, WM, MM), pp. 141–145.
DATE-2000-GirolaPV: Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing (UG, AP, DV), pp. 181–185.
DATE-2000-GuerrierG #architecture: A Generic Architecture for On-Chip Packet-Switched Interconnections (PG, AG), pp. 250–256.
DATE-2000-HenkeGV #design #estimation #performance: Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design (JH, TG, FV), pp. 333–338.
DATE-2000-HuangOC #testing: A BIST Scheme for On-Chip ADC and DAC Testing (JLH, CKO, KTC), pp. 216–220.
DATE-2000-ItoCJ #design #java: System Design Based on Single Language and Single-Chip Java ASIP Microcontroller (SAI, LC, RPJ), pp. 703–707.
DATE-2000-LajoloRDL #design #performance: Efficient Power Co-Estimation Techniques for System-on-Chip Design (ML, AR, SD, LL), pp. 27–34.
DATE-2000-SuCHCL #metric: All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses (CS, YTC, MJH, GNC, CLL), pp. 527–531.
DATE-2000-WenL: An on Chip ADC Test Structure (YCW, KJL), pp. 221–225.
CC-2000-WangTP #framework #memory management: A Framework for Loop Distribution on Limited On-Chip Memory Processors (LW, WT, SP), pp. 141–156.
HPCA-2000-BarrosoGNV #integration #performance: Impact of Chip-Level Integration on Performance of OLTP Workloads (LAB, KG, AN, BV), pp. 3–14.
DAC-1999-ChenM #using: Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (CPC, NM), pp. 502–506.
DAC-1999-ClementHLRCP #design #multi #performance #prototype: Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design (BC, RH, EL, BR, PC, FP), pp. 420–424.
DAC-1999-GeistBASNFHLKB #verification: A Methodology for the Verification of a “System on Chip” (DG, GB, TA, MS, YN, MF, KH, AL, DK, SB), pp. 574–579.
DAC-1999-Morton #multi: On-Chip Inductance Issues in Multiconductor Systems (SVM), pp. 921–926.
DAC-1999-PapachristouMN #testing: Microprocessor Based Testing for Core-Based System on Chip (CAP, FM, MN), pp. 586–591.
DAC-1999-PomerleauFB #predict: Improved Selay Prediction for On-Chip Buses (RGP, PDF, GLB), pp. 497–501.
DAC-1999-RestleRW #design #performance: Dealing with Inductance in High-Speed Chip Design (PR, AER, SGW), pp. 904–909.
DAC-1999-SuWL #interactive: A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning (HPS, ACHW, YLL), pp. 262–267.
DAC-1999-YueW #design: Design Strategy of On-Chip Inductors for Highly Integrated RF Systems (CPY, SSW), pp. 982–987.
DATE-1999-BolsensMDBV #hybrid #integration: Single Chip or Hybrid System Integration (IB, WM, LD, JB, HJMV), p. 616–?.
DATE-1999-DickJ #multi #named #synthesis: MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis (RPD, NKJ), pp. 263–270.
DATE-1999-FeldmanKL #modelling #performance: Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics (PF, SK, DEL), pp. 418–417.
DATE-1999-OchiaiINEO #embedded #framework #performance #video: High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit (KO, HI, JN, ME, TO), pp. 303–308.
DATE-1999-SantosT #fault #simulation #using: Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL (MBS, JPT), p. 549–?.
DATE-1999-StopjakovaMS #monitoring #testing: On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC (VS, HARM, MS), pp. 538–542.
DATE-1999-Troster #co-evolution #design #performance: Potentials of Chip-Package Co-Design for High-Speed Digital Applications (GT), pp. 423–422.
DATE-1999-YeCFCNC #design #verification: Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs (LY, FCC, PF, RC, NN, FC), pp. 658–663.
AdaEurope-1999-Mermet #design #specification #standard: System on Chip Specification and Design Languages Standardization (JM), pp. 371–384.
HPCA-1999-InoueKM #logic #memory management: Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs (KI, KK, KM), pp. 218–222.
DAC-1998-GhoshDJ #low cost #performance #testing: A Fast and Low Cost Testing Technique for Core-Based System-on-Chip (IG, SD, NKJ), pp. 542–547.
DAC-1998-IsmailFN: Figures of Merit to Characterize the Importance of On-Chip Inductance (YII, EGF, JLN), pp. 560–565.
DAC-1998-KimCLLPK #functional #modelling: Virtual Chip: Making Functional Models Work on Real Target Systems (NK, HC, SL, SL, ICP, CMK), pp. 170–173.
DAC-1998-KrauterM #analysis #layout: Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis (BK, SM), pp. 303–308.
DAC-1998-MassoudMBW #layout: Layout Techniques for Minimizing On-Chip Interconnect Self Inductance (YM, SSM, TB, JW), pp. 566–571.
DAC-1998-NassifDH #modelling #robust #verification: Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.
DAC-1998-RaelRA #design: Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver (JR, AR, AAA), pp. 44–49.
DAC-1998-SteeleORH #verification: Full-Chip Verification Methods for DSM Power Distribution Systems (GS, DO, SR, SZH), pp. 744–749.
DAC-1998-Zorian #tutorial: System-Chip Test Strategies (Tutorial) (YZ), pp. 752–757.
DATE-1998-EpplerFGM #energy #network #physics: High Speed Neural Network Chip for Trigger Purposes in High Energy Physics (WE, TF, HG, AM), pp. 108–115.
DATE-1998-Loore #design: IP-Based System-on-a-Chip Design (BdL), p. 290.
DATE-1998-Neely #configuration management #logic: Reconfigurable Logic for Systems on a Chip (WSN), p. 340.
DATE-1998-StrakaMVS #metric: A Fully Digital Controlled Off-Chip IDDQ Measurement Unit (BS, HARM, JV, MS), pp. 495–500.
DATE-1998-SvajdaSM #metric #named: IOCIMU — An Integrated Off-Chip IDDQ Measurement Unit (MS, BS, HARM), pp. 959–960.
DATE-1998-X #debugging: Silicon Debug of Systems-on-Chips, pp. 632–633.
FM-1998-FujitaRH #case study #experience #parallel #protocol #verification: Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol (MF, SPR, AJH), pp. 281–295.
FM-1998-GeserK #verification: Structured Formal Verification of a Fragment of the IBM S/390 Clock Chip (AG, WK), pp. 92–106.
ASPLOS-1998-HammondWO #multi: Data Speculation Support for a Chip Multiprocessor (LH, MW, KO), pp. 58–69.
HPCA-1998-KatevenisSS: Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch (MK, DNS, ES), pp. 47–56.
DAC-1997-ChenL #analysis #design #power management: Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design (HHC, DDL), pp. 638–643.
DAC-1997-Dai #verification: Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract) (WWMD), pp. 717–719.
EDTC-1997-AbdullaRK #embedded #multi: A scheme for multiple on-chip signature checking for embedded SRAMs (MFA, CPR, AK), p. 625.
EDTC-1997-FauraHKCAI #integration #programmable: A new field programmable system-on-a-chip for mixed signal integration (JF, CH, BK, JC, MAA, JMI), p. 610.
EDTC-1997-Gonzalez-TorresMH #set: Full custom chip set for high speed serial communications up to 2.48 Gbit/s (JGT, PAM, JMH), p. 614.
EDTC-1997-KunduG #analysis: Inductance analysis of on-chip interconnects [deep submicron CMOS] (SK, UG), pp. 252–255.
EDTC-1997-LiuS #graph #heuristic #multi #performance #using: Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic (LCEL, CS), pp. 311–318.
EDTC-1997-RenovellAB: On-chip analog output response compaction (MR, FA, YB), pp. 568–572.
EDTC-1997-SvajdaSM #monitoring: A monolithic off-chip IDDQ monitor (MS, BS, HARM), p. 629.
DAC-1996-ChengTDRK #named #reliability: iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips (YKC, CCT, AD, ER, SMK), pp. 548–551.
DAC-1996-DesaiCJ #cpu #network #performance: Sizing of Clock Distribution Networks for High Performance CPU Chips (MPD, RC, JJ), pp. 389–394.
SAC-1996-GabrielliGM #design #fuzzy #process: VLSI design of a fuzzy chip that processes 2-4 inputs every 160-320 ns whichever is the fuzzy system (AG, EG, MM), pp. 590–594.
ASPLOS-1996-OlukotunNHWC #multi: The Case for a Single-Chip Multiprocessor (KO, BAN, LH, KGW, KC), pp. 2–11.
HPCA-1996-TakahashiTKS #multi #protocol: A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor (MT, HT, EK, SS), pp. 314–322.
SAC-1995-KumblaJB #algorithm #fuzzy #implementation #logic #network #using: Implementation of fuzzy logic and neural networks control algorithm using a digital signal processing chip (KKK, MJ, JBR), pp. 524–528.
DAC-1994-GuptaCDP #design #experience #image #tool support #using: Experience with Image Compression Chip Design using Unified System Construction Tools (PG, CTC, JCDB, ACP), pp. 250–256.
DAC-1994-LanZG #multi #programmable: Placement and Routing for a Field Programmable Multi-Chip Module (SL, AZ, AEG), pp. 295–300.
EDAC-1994-ChenYF #debugging #design #identification #model checking: Bug Identification of a Real Chip Design by Symbolic Model Checking (BC, MY, MF), pp. 132–136.
EDAC-1994-Saucier #design #network #recognition: Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network (DJ, GS), pp. 256–260.
DAC-1993-DaoMHOM: A Compaction Method for Full Chip VLSI Layouts (JD, NM, TH, CO, SM), pp. 407–412.
ICLP-1993-BisdorffL #industrial #problem: Industrial Disposing Problem Solved in CHIP (RB, SL), p. 831.
ILPS-1993-BoizumaultDP #problem #using: Solving a real life exams problem using CHIP (PB, YD, LP), p. 661.
DAC-1992-Gebotys #embedded #scheduling: Optimal Scheduling and Allocation of Embedded VLSI Chips (CHG), pp. 116–119.
DAC-1992-HungP #constraints #design #multi #synthesis: High-Level Synthesis with Pin Constraints for Multiple-Chip Designs (YHH, ACP), pp. 231–234.
DAC-1992-ShihKT #clustering #multi: Performance-Driven System Partitioning on Multi-Chip Modules (MS, ESK, RST), pp. 53–56.
DAC-1991-EnbodyLT #3d: Routing the 3-D Chip (RJE, GL, KHT), pp. 132–137.
ICALP-1991-DurisG #multi #on the #power of: On the Power of Multiple Reads in a Chip (PD, ZG), pp. 697–706.
ICLP-1991-AggounB #bibliography #compilation: Overview of the CHIP Compiler System (AA, NB), pp. 775–789.
DAC-1990-ChatterjeeH #approach #clustering: A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing (AC, RIH), pp. 36–39.
DAC-1990-Ito #automation #testing: Automatic Incorporation of On-Chip Testability Circuits (NI), pp. 529–534.
DAC-1990-Wang #layout: Pad Placement and Ring Routing for Custom Chip Layout (DCW), pp. 193–199.
ALP-1990-SimonisD #calculus #problem: Propositional Calculus Problems in CHIP (HS, MD), pp. 189–203.
DAC-1989-BruceMH #multi: Multi Chip Modules (RHB, WPM, JH), pp. 389–393.
DAC-1989-LukD #layout #multi #optimisation: Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout (WKL, AAD), pp. 110–115.
DAC-1988-BaileyS #empirical #parallel: An Empirical Study of On-chip Parallelism (MLB, LS), pp. 160–165.
DAC-1988-BergstraesserGHW #architecture #named #synthesis #tool support: SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture (TB, JG, KH, SW), pp. 654–657.
DAC-1988-ChaoG #fault #modelling: Micro-operation Perturbations in Chip Level Fault Modeling (CHC, FGG), pp. 579–582.
DAC-1988-GedyeK #database #design: Browsing in Chip Design Database (DG, RHK), pp. 269–274.
DAC-1988-NarendranS #image #verification: Formal Verification of the Sobel Image Processing Chip (PN, JS), pp. 211–217.
DAC-1988-Sechen #metaprogramming #using: Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing (CS), pp. 73–80.
CADE-1988-DincbasHSAH #constraints #prolog: The CHIP System: Constraint Handling In Prolog (MD, PVH, HS, AA, AH), pp. 774–775.
SIGIR-1987-MukherjeeB #performance #retrieval: A VLSI Chip for Efficient Transmission and Retrieval of Information (AM, MAB), pp. 208–216.
DAC-1986-BarclayA #algorithm #generative #heuristic #testing: A heuristic chip-level test generation algorithm (DSB, JRA), pp. 257–262.
DAC-1986-HaugeY #design #named #physics: Vanguard: a chip physical design system (PSH, EJY), pp. 440–446.
DAC-1986-LukTW #design: Hierarchial global wiring for custom chip design (WKL, DTT, CKW), pp. 481–489.
DAC-1986-PutatundaSMC #compilation #named: HAPPI: a chip compiler based on double-level-metal technology (RP, DS, SM, JC), pp. 736–743.
DAC-1986-Wolf #database #object-oriented: An object-oriented, procedural database for VLSI chip planning (WW), pp. 744–751.
LFP-1986-Ramsdell: The CURRY Chip (JDR), pp. 122–131.
DAC-1985-AnwayFR #layout: PLINT layout system for VLSI chips (HA, GF, RR), pp. 449–452.
DAC-1984-DasguptaGRWW #clustering #design #testing: Chip partitioning aid: A design technique for partitionability and testability in VLSI (SD, MCG, RAR, RGW, TWW), pp. 203–208.
DAC-1984-DunlopADJKW #layout #optimisation #using: Chip layout optimization using critical path weighting (AED, VDA, DND, MFJ, PK, MW), pp. 133–136.
DAC-1984-DussaultLT #design #synthesis: A high level synthesis tool for MOS chip design (JPD, CCL, MMT), pp. 308–314.
DAC-1984-Freund #design #scalability #testing: Managing a large volume of design/manufacturing/test data in a chip and module factory (VJFJ), pp. 447–451.
DAC-1984-RaoRZ: Spider, a chip planner for ISL technology (PR, RR, GZ), pp. 665–666.
DAC-1984-SchnurmannVP #automation #memory management #testing: An automated system for testing LSI memory chips (HDS, LJV, RMP), pp. 454–458.
DAC-1984-Trimberger #assembly #named #visual notation: VTIcompose — a powerful graphical chip assembly tool (ST), pp. 697–698.
DAC-1983-AhdootAC #design: IBM FSD VLSI chip design methodology (KA, RRA, LC), pp. 39–45.
DAC-1983-GranackiP #design #performance #trade-off: The effect of register-transfer design tradeoffs on chip area and performance (JJG, ACP), pp. 419–424.
DAC-1983-KatzW #concept: Chip assemblers: Concepts and capabilities (RHK, SW), pp. 25–30.
DAC-1983-Moulton: Laying the power and ground wires on a VLSI chip (ASM), pp. 754–755.
DAC-1982-AdachiKNS #design #layout #top-down: Hierarchical top-down layout design method for VLSI chip (TA, HK, MN, TS), pp. 785–791.
DAC-1982-GoelM: Electronic Chip-in-Place Test (PG, MTM), pp. 482–488.
DAC-1982-KangKL #adaptation #cpu #design #evolution #layout #logic #matrix #random: Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design (SMK, RHK, HFSL), pp. 170–174.
DAC-1982-Putatunda #automation #named: Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips (RP), pp. 616–621.
DAC-1982-TrimbergerR #assembly #named #visual notation: Riot — a simple graphical chip assembly tool (ST, JAR), pp. 371–376.
ASPLOS-1982-FusaokaH #compilation #hardware #implementation: Compiler Chip: A Hardware Implementation of Compiler (AF, MH), pp. 92–95.
STOC-1980-BrentK #complexity: The Chip Complexity of Binary Arithmetic (RPB, HTK), pp. 190–200.
DAC-1979-LallierJ: A new circuit placement program for FET chips (KWL, RKJ), pp. 109–113.
DAC-1979-WangB #automation: A software system for Automated Placement And Wiring of LSI chips (PTW, PB), pp. 327–329.
DAC-1978-KoppelSP #logic #performance: A high performance delay calculation software system for MOSFET digital logic chips (AK, SS, PP), pp. 405–417.
DAC-1977-AguleLRS #optimisation: An experimental system for power/timing optimization of LSI chips (BJA, JDL, AER, PKWS), pp. 147–152.
DAC-1977-ChenFKNS #automation #layout #problem: The chip layout problem: An automatic wiring procedure (KAC, MF, KHK, NN, SS), pp. 298–302.
DAC-1977-KhokhaniP #layout #problem: The chip layout problem: A placement procedure for lsi (KHK, AMP), pp. 291–297.
DAC-1974-Wang #algorithm #clustering: A partitioning technique for LSI chips including a bunching algorithm (PTW), p. 91.
DAC-1970-Farlow #design: Machine aids to the design of ceramic substrates containing integrated circuit chips (CWF), pp. 274–285.
DAC-1970-Spitalny #design: Designing a system on a chip (AS), pp. 336–345.