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Travelled to:
1 × France
1 × Germany
Collaborated with:
A.Yakovlev D.Sokolov M.Koutny A.Madalinski V.Khomenko
Talks about:
asynchron (2) circuit (2) visual (2) design (2) conflict (1) resolut (1) partial (1) optimis (1) direct (1) order (1)

Person: Alexandre V. Bystrov

DBLP DBLP: Bystrov:Alexandre_V=

Contributed to:

DATE 20032003
DATE 20022002

Wrote 3 papers:

DATE-2003-MadalinskiBKY #design #visualisation
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design (AM, AVB, VK, AY), pp. 10926–10931.
DATE-2003-SokolovBY #optimisation
STG Optimisation in the Direct Mapping of Asynchronous Circuits (DS, AVB, AY), pp. 10932–10939.
DATE-2002-BystrovKY #design #modelling #partial order #visualisation
Visualization of Partial Order Models in VLSI Design Flow (AVB, MK, AY), p. 1089.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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