BibSLEIGH — Alexandre

Travelled to:

3 × Germany
4 × USA
5 × France

Collaborated with:

A.V.Bystrov A.Kondratyev J.Cortadella M.Kishinevsky A.L.Semenov D.Sokolov M.Koutny L.Lavagno F.P.Burns V.Khomenko B.Halak A.Mokhov S.Dasgupta T.S.T.Mak F.Xia A.Karkar K.Tong D.Shang A.Koelmans A.Madalinski R.Al-Dujaily M.Palesi E.Pastor M.A.Peña B.Lin P.Vanbekbergen A.Iliasov A.Rafiev R.Gensh A.Romanovsky S.Ogg E.Valli B.M.Al-Hashimi C.D'Alessandro L.Benini

Talks about:

asynchron (8) circuit (7) synthesi (6) use (4) independ (3) partial (3) verif (3) speed (3) model (3) conflict (2)

Person: Alexandre Yakovlev

DBLP: Yakovlev:Alexandre

Contributed to:

2015

2011

2008

2005

2004

2003

2002

1999

1997

1996

1994

Wrote 19 papers:

DATE-2015-BurnsSY #modelling #synthesis #verification: GALS synthesis and verification for xMAS models (FPB, DS, AY), pp. 1419–1424.
DATE-2015-KarkarTMY #communication #distributed #multi: Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting (AK, KFT, TSTM, AY), pp. 794–799.
PDP-2015-IliasovRXGRY #manycore #prototype #specification: A Formal Specification and Prototyping Language for Multi-core System Management (AI, AR, FX, RG, AR, AY), pp. 696–700.
DATE-2011-Al-DujailyMXYP #concurrent #detection #network #runtime #transitive #using: Run-time deadlock detection in networks-on-chip using coupled transitive closure networks (RAD, TSTM, FX, AY, MP), pp. 497–502.
DATE-2008-HalakY #optimisation: Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods (BH, AY), pp. 438–443.
DATE-2008-MokhovY #configuration management #graph #partial order #synthesis: Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis (AM, AY), pp. 1142–1147.
DATE-2008-OggVAYDB: Serialized Asynchronous Links for NoC (SO, EV, BMAH, AY, CD, LB), pp. 1003–1008.
DATE-2005-DasguptaY #architecture #modelling #verification: Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures (SD, AY), pp. 568–569.
DATE-v1-2004-BurnsSKY #synthesis #tool support #using: An Asynchronous Synthesis Toolset Using Verilog (FPB, DS, AK, AY), pp. 724–725.
DATE-2003-MadalinskiBKY #design #visualisation: Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design (AM, AVB, VK, AY), pp. 10926–10931.
DATE-2003-SokolovBY #optimisation: STG Optimisation in the Direct Mapping of Asynchronous Circuits (DS, AVB, AY), pp. 10932–10939.
DATE-2002-BystrovKY #design #modelling #partial order #visualisation: Visualization of Partial Order Models in VLSI Design Flow (AVB, MK, AY), p. 1089.
DATE-2002-KhomenkoKY #detection #integer #programming #using: Detecting State Coding Conflicts in STGs Using Integer Programming (VK, MK, AY), pp. 338–345.
DAC-1999-KondratyevCKLY #automation #optimisation #synthesis: Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems (AK, JC, MK, LL, AY), pp. 110–115.
DAC-1997-SemenovYPPC #independence #synthesis: Synthesis of Speed-Independent Circuits from STG-Unfolding Segment (ALS, AY, EP, MAP, JC), pp. 16–21.
EDTC-1997-CortadellaKKLY #composition #independence: Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis (JC, MK, AK, LL, AY), pp. 98–105.
DAC-1996-CortadellaKKLY #encoding #synthesis #tool support: Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis (JC, MK, AK, LL, AY), pp. 63–66.
DAC-1996-SemenovY #petri net #using #verification: Verification of asynchronous circuits using Time Petri Net unfolding (ALS, AY), pp. 59–62.
DAC-1994-KondratyevKLVY #implementation #independence: Basic Gate Implementation of Speed-Independent Circuits (AK, MK, BL, PV, AY), pp. 56–62.