BibSLEIGH — Proceedings of the Eighth Conference on Design, Automation and Test in Europe

Proceedings of the Eighth Conference on Design, Automation and Test in Europe
DATE, 2003.

SYS

@proceedings{DATE-2003,
	address       = "Munich, Germany",
	isbn          = "0-7695-1870-2",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Eighth Conference on Design, Automation and Test in Europe}",
	year          = 2003,
}

Contents (267 items)

DATE-2003-AartsR #challenge #design: IC Design Challenges for Ambient Intelligence (EHLA, RR), pp. 10002–10007.
DATE-2003-Cuomo #challenge: Semiconductor Challenges (AC), pp. 10008–10009.
DATE-2003-LindwerMBZMJC #concept: Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts (ML, DM, TB, RZ, RM, SJ, EC), pp. 10010–10017.
DATE-2003-MaciiMP #clustering #memory management #performance: Improving the Efficiency of Memory Partitioning by Address Clustering (AM, EM, MP), pp. 10018–10023.
DATE-2003-MaciiMCZ #algorithm #embedded #energy: A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors (AM, EM, FC, RZ), pp. 10024–10029.
DATE-2003-PetrovO #memory management #performance: Power Efficiency through Application-Specific Instruction Memory Transformations (PP, AO), pp. 10030–10035.
DATE-2003-Sanchez-ElezFADBH #architecture #configuration management #data transformation #energy #memory management #multi: Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures (MSE, MF, MLA, HD, NB, RH), pp. 10036–10043.
DATE-2003-GrundmannGK #challenge #design #framework #platform: Circuit and Platform Design Challenges in Technologies beyond 90nm (BG, RG, SK), pp. 10044–10049.
DATE-2003-HuangCW #nondeterminism: Global Wire Bus Configuration with Minimum Delay Uncertainty (LDH, HMC, DFW), pp. 10050–10055.
DATE-2003-Zhou #verification: Timing Verification with Crosstalk for Transparently Latched Circuits (HZ), pp. 10056–10061.
DATE-2003-AgarwalBZV #analysis #bound #statistics #using: Statistical Timing Analysis Using Bounds (AA, DB, VZ, SBKV), pp. 10062–10067.
DATE-2003-VelenisPF #network #nondeterminism #performance: Reduced Delay Uncertainty in High Performance Clock Distribution Networks (DV, MCP, EGF), pp. 10068–10075.
DATE-2003-BastenBCLLMZ #scalability: Scaling into Ambient Intelligence (TB, LB, AC, ML, JL, RM, FZ), pp. 10076–10083.
DATE-2003-SaputraVKIBKZ #behaviour #encryption #energy: Masking the Energy Behavior of DES Encryption (HS, NV, MTK, MJI, RRB, SK, WZ), pp. 10084–10089.
DATE-2003-WuAE #embedded #graph #power management #scheduling #synthesis: Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems (DW, BMAH, PE), pp. 10090–10095.
DATE-2003-ChiouBR #multi #power management #synthesis: Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications (LYC, SB, KR), pp. 10096–10103.
DATE-2003-RaoO #design: Virtual Compression through Test Vector Stitching for Scan Based Designs (WR, AO), pp. 10104–10109.
DATE-2003-OhKWS #architecture #feedback #using: Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture (NO, RK, TWW, JS), pp. 10110–10115.
DATE-2003-KnieserWPWM: A Technique for High Ratio LZW Compression (MJK, FGW, CAP, DJW, DRM), pp. 10116–10121.
DATE-2003-ZengZHC #correlation #performance #using: Fast Computation of Data Correlation Using BDDs (ZZ, QZ, IGH, MJC), pp. 10122–10129.
DATE-2003-GerstlauerYG #design #modelling: RTOS Modeling for System Level Design (AG, HY, DG), pp. 10130–10135.
DATE-2003-WangMB #embedded #integration #modelling: Modeling and Integration of Peripheral Devices in Embedded Systems (SW, SM, RAB), pp. 10136–10141.
DATE-2003-HerreraPSV #embedded #generative: Systemic Embedded Software Generation from SystemC (FH, HP, PS, EV), pp. 10142–10149.
DATE-2003-XuLLP #megamodelling: Noise Macromodel for Radio Frequency Integrated Circuits (YX, XL, PL, LTP), pp. 10150–10155.
DATE-2003-GouraryRUZGM #approach #approximate: Approximation Approach for Timing Jitter Characterization in Circuit Simulators (MMG, SGR, SLU, MMZ, KKG, BJM), pp. 10156–10161.
DATE-2003-MartensG: A Model of Computation for Continuous-Time ?-? Modulators (EM, GGEG), pp. 10162–10167.
DATE-2003-Castro-LopezFMR #behaviour #hardware #modelling #simulation #using: Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages (RCL, FVF, FM, ÁRV), pp. 10168–10175.
DATE-2003-RaghunathanRHQ #challenge #design #mobile: Securing Mobile Appliances: New Challenges for the System Designer (AR, SR, SH, JJQ), pp. 10176–10183.
DATE-2003-PopEP #analysis #clustering #distributed #embedded #multi #optimisation #scheduling #synthesis: Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems (PP, PE, ZP), pp. 10184–10189.
DATE-2003-ChakrabortyKT #design #embedded #framework #platform: A General Framework for Analysing System Properties in Platform-Based Embedded System Designs (SC, SK, LT), pp. 10190–10195.
DATE-2003-LogothetisS #analysis #source code: Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration (GL, KS), pp. 10196–10203.
DATE-2003-RinnerSW #agile #architecture #embedded #flexibility #multi #prototype: Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures (BR, MS, RW), pp. 10204–10211.
DATE-2003-NummerS #pipes and filters #testing: DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers (MN, MS), pp. 10212–10217.
DATE-2003-AhmedTN #testing: Extending JTAG for Testing Signal Integrity in SoCs (NA, MHT, MN), pp. 10218–10223.
DATE-2003-PradhanLC #detection #fault #generative #named #novel: EBIST: A Novel Test Generator with Built-In Fault Detection Capability (DKP, CL, KC), pp. 10224–10229.
DATE-2003-LiuC #approach #fault #identification: A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis (CL, KC), pp. 10230–10237.
DATE-2003-VanasscheGS #analysis #detection #domain model #modelling: Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors (PV, GGEG, WMCS), pp. 10238–10243.
DATE-2003-GouraryRUZM #analysis #simulation: A New Simulation Technique for Periodic Small-Signal Analysis (MMG, SGR, SLU, MMZ, BJM), pp. 10244–10249.
DATE-2003-EeckelaertDGS #modelling #performance: Generalized Posynomial Performance Modeling (TE, WD, GGEG, WMCS), pp. 10250–10255.
DATE-2003-SmedtG #bound #design #named: HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits (BDS, GGEG), pp. 10256–10263.
DATE-2003-MolinaMH #hardware: High-Level Allocation to Minimize Internal Hardware Wastage (MCM, JMM, RH), pp. 10264–10269.
DATE-2003-GuptaDGN #branch #design #synthesis: Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs (SG, NDD, RKG, AN), pp. 10270–10275.
DATE-2003-KimSLLNN #data flow #distributed #graph: Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units (EK, HS, JGL, DIL, HN, TN), pp. 10276–10281.
DATE-2003-RyuM #automation #design #generative #multi: Automated Bus Generation for Multiprocessor SoC Design (KKR, VJM), pp. 10282–10289.
DATE-2003-WalderP #configuration management #online #scheduling: Online Scheduling for Block-Partitioned Reconfigurable Devices (HW, MP), pp. 10290–10295.
DATE-2003-MeiVVML #architecture #configuration management #parallel #scheduling #using: Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling (BM, SV, DV, HDM, RL), pp. 10296–10301.
DATE-2003-LangeK #configuration management #design #embedded #framework #hardware #platform: Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems (SL, UK), pp. 10302–10309.
DATE-2003-OhtakeOF #algorithm #fault #generative #testing #using: A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms (SO, KO, HF), pp. 10310–10315.
DATE-2003-SyalH #algorithm #fault #identification #low cost #novel: A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification (MS, MSH), pp. 10316–10321.
DATE-2003-PadmanabanT #fault: Non-Enumerative Path Delay Fault Diagnosis (SP, ST), pp. 10322–10327.
DATE-2003-KrsticWCLA #fault #modelling #statistics: Delay Defect Diagnosis Based Upon Statistical Timing Models — The First Step (AK, LCW, KTC, JJL, MSA), pp. 10328–10335.
DATE-2003-YooJ #abstraction #hardware: Introduction to Hardware Abstraction Layers for SoC (SY, AAJ), pp. 10336–10337.
DATE-2003-Mooney #clustering #hardware #operating system: Hardware/Software Partitioning of Operating Systems (VJM), pp. 10338–10339.
DATE-2003-SarlotteCQM #embedded: Embedded Software in Digital AM-FM Chipset (MS, BC, JQ, DM), pp. 10340–10343.
DATE-2003-YeBM #analysis #communication: Packetized On-Chip Interconnect Communication Analysis for MPSoC (TTY, LB, GDM), pp. 10344–10349.
DATE-2003-RijpkemaGRDMWW #design #network: Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip (ER, KGWG, AR, JD, JLvM, PW, EW), pp. 10350–10355.
DATE-2003-GilbertTW #architecture #communication #embedded #multi: Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors (FG, MJT, NW), pp. 10356–10363.
DATE-2003-SanderJL #design #development: Development and Application of Design Transformations in ForSyDe (IS, AJ, ZL), pp. 10364–10369.
DATE-2003-Singh #specification: System Level Specification in Lava (SS), pp. 10370–10375.
DATE-2003-Salem #semantics: Formal Semantics of Synchronous SystemC (AS), pp. 10376–10381.
DATE-2003-DoucetSG #framework: Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated (FD, SKS, RKG), pp. 10382–10387.
DATE-2003-VachouxGE #design #requirements: SystemC-AMS Requirements, Design Objectives and Rationale (AV, CG, KE), pp. 10388–10395.
DATE-2003-Vissers #architecture #configuration management #parallel: Parallel Processing Architectures for Reconfigurable Systems (KAV), pp. 10396–10397.
DATE-2003-GuptaB #architecture: Different Approaches to Add Reconfigurability in a SoC Architecture (BG, MB), p. 10398.
DATE-2003-BlodgetML #approach #configuration management #embedded #lightweight: A Lightweight Approach for Embedded Reconfiguration of FPGAs (BB, SM, PL), pp. 10399–10401.
DATE-2003-MarinissenVMKM: Creating Value Through Test (EJM, BV, RM, MK, MM), pp. 10402–10409.
DATE-2003-FalkM #control flow #source code: Control Flow Driven Splitting of Loop Nests at the Source Code Level (HF, PM), pp. 10410–10415.
DATE-2003-KandemirCZK #embedded #scheduling: Data Space Oriented Scheduling in Embedded Systems (MTK, GC, WZ, IK), pp. 10416–10421.
DATE-2003-PillaiJ #clustering #scheduling: Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling (SP, MFJ), pp. 10422–10427.
DATE-2003-LomenaLWK #approach #explosion #performance #scheduling: An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling (AGL, MLLV, YW, AK), pp. 10428–10435.
DATE-2003-WestraJOV: Time Budgeting in a Wireplanning Context (JW, DJJ, RHJMO, CV), pp. 10436–10441.
DATE-2003-LuK: Interconnect Planning with Local Area Constrained Retiming (RL, CKK), pp. 10442–10447.
DATE-2003-DasguptaKM #architecture #metric #novel #performance: A Novel Metric for Interconnect Architecture Performance (PD, ABK, SM), pp. 10448–10455.
DATE-2003-ZhuM #component #non-functional #specification: Specification of Non-Functional Intellectual Property Components (JZ, WSM), pp. 10456–10461.
DATE-2003-XieWL: Profile-Driven Selective Code Compression (YX, WW, HL), pp. 10462–10467.
DATE-2003-PanBKK #analysis #architecture #design #programmable: Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver (CP, NB, AHK, AK), pp. 10468–10475.
DATE-2003-LupeaPJ #analysis #named: RF-BIST: Loopback Spectral Signature Analysis (DL, UP, HJJ), pp. 10478–10483.
DATE-2003-Al-ArsGBR #fault #optimisation #simulation #testing #using: Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation (ZAA, AJvdG, JB, DR), pp. 10484–10489.
DATE-2003-ZachariahCKT #fault #modelling #on the: On Modeling Cross-Talk Faults (STZ, YSC, SK, CT), pp. 10490–10495.
DATE-2003-BurbidgeTR #automation #embedded #monitoring: Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops (MJB, JT, AR), pp. 10496–10503.
DATE-2003-RapakaM #analysis #embedded #performance: Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications (VSPR, DM), pp. 10504–10509.
DATE-2003-KandemirZK #parallel #runtime: Runtime Code Parallelization for On-Chip Multiprocessors (MTK, WZ, MK), pp. 10510–10515.
DATE-2003-MarchalGPBBCC #energy #memory management #multi #platform: SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms (PM, JIG, LP, DB, LB, FC, HC), pp. 10516–10523.
DATE-2003-MartorellMA #evaluation #modelling: Modeling and Evaluation of Substrate Noise Induced by Interconnects (FM, DM, XA), pp. 10524–10529.
DATE-2003-MansourM #reduction: Model-Order Reduction Based on PRONY’s Method (MMM, AM), pp. 10530–10535.
DATE-2003-Grivet-TalociaSMC #megamodelling #simulation: Combined FDTD/Macromodel Simulation of Interconnected Digital Devices (SGT, ISS, IAM, FGC), pp. 10536–10541.
DATE-2003-LvHLW #encoding: Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses (TL, JH, HL, WW), pp. 10542–10549.
DATE-2003-YooBBPJ #abstraction #hardware #modelling #performance #simulation: Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer (SY, IB, AB, YP, AAJ), pp. 10550–10555.
DATE-2003-QinM #flexibility #formal method #modelling #simulation: Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation (WQ, SM), pp. 10556–10561.
DATE-2003-SchnerrHR #agile #prototype #set: Instruction Set Emulation for Rapid Prototyping of SoCs (JS, GH, WR), pp. 10562–10569.
DATE-2003-RosaLP #configuration management #design #hardware: Hardware/Software Design Space Exploration for a Reconfigurable Processor (ALR, LL, CP), pp. 10570–10575.
DATE-2003-CardosoW #c #source code: From C Programs to the Configure-Execute Model (JMPC, MW), pp. 10576–10581.
DATE-2003-MazzeoRSM #implementation: FPGA-Based Implementation of a Serial RSA Processor (AM, LR, GPS, NM), pp. 10582–10589.
DATE-2003-NicolaidisAB #configuration management #self: Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair (MN, NA, SB), pp. 10590–10595.
DATE-2003-OikonomakosZA #metric #online #self #synthesis #testing #using: Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric (PO, MZ, BMAH), pp. 10596–10601.
DATE-2003-RebaudengoRV #analysis #fault #pipes and filters: An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor (MR, MSR, MV), pp. 10602–10607.
DATE-2003-OmanaRM #parallel: High Speed and Highly Testable Parallel Two-Rail Code Checker (MO, DR, CM), pp. 10608–10615.
DATE-2003-TindellKWE #development: Safe Automotive Software Development (KT, HK, FW, RE), pp. 10616–10623.
DATE-2003-DobrovolnyVWD #analysis #modelling: Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits (PD, GV, PW, SD), pp. 10624–10629.
DATE-2003-WegenerK #fault #identification #linear #modelling: Linear Model-Based Error Identification and Calibration for Data Converters (CW, MPK), pp. 10630–10635.
DATE-2003-AlbiolGA #design #performance: Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters (MA, JLG, EA), pp. 10636–10641.
DATE-2003-EberleVWDGM #automation #behaviour #modelling #simulation: Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver (WE, GV, PW, SD, GGEG, HDM), pp. 10642–10649.
DATE-2003-GhoshG #design #embedded: Analytical Design Space Exploration of Caches for Embedded Systems (AG, TG), pp. 10650–10655.
DATE-2003-ZivkovicKWD #architecture #multi #performance #source code: Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs (VDZ, EAdK, PvdW, EFD), pp. 10656–10661.
DATE-2003-VanzagoBCL #configuration management #design #framework #platform #protocol: Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform (LV, BB, JC, LL), pp. 10662–10667.
DATE-2003-FornaciariMSZ #clustering #specification #towards #uml: A First Step Towards Hw/Sw Partitioning of UML Specifications (WF, PM, FS, LZ), pp. 10668–10673.
DATE-2003-MoullecADAP #metric #multi #personalisation: Multi-Granularity Metrics for the Era of Strongly Personalized SOCs (YLM, NBA, JPD, MA, JLP), pp. 10674–10681.
DATE-2003-FeiRRJ #energy #estimation: Energy Estimation for Extensible Processors (YF, SR, AR, NKJ), pp. 10682–10687.
DATE-2003-HuM #architecture #energy #flexibility #performance: Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures (JH, RM), pp. 10688–10693.
DATE-2003-ChengP #encoding #interface #power management #visual notation: Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface (WCC, MP), pp. 10694–10699.
DATE-2003-ChooMR #architecture #named #power management #synthesis: MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters (HC, KM, KR), pp. 10700–10705.
DATE-2003-BertozziRBR #embedded #energy #optimisation #performance #protocol: Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems (DB, AR, LB, SR), pp. 10706–10713.
DATE-2003-KranitisXGPZ #low cost #self: Low-Cost Software-Based Self-Testing of RISC Processor Cores (NK, GX, DG, AMP, YZ), pp. 10714–10719.
DATE-2003-BernardiRRV #approach #embedded #programmable: A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories (PB, MR, MSR, MV), pp. 10720–10725.
DATE-2003-GonciariAN #perspective #testing: Test Data Compression: The System Integrator’s Perspective (PTG, BMAH, NN), pp. 10726–10731.
DATE-2003-EbadiI #comparison #implementation #multi: Time Domain Multiplexed TAM: Implementation and Comparison (ZSE, AI), pp. 10732–10737.
DATE-2003-GoelM #architecture #design: Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization (SKG, EJM), pp. 10738–10741.
DATE-2003-XuN #fault #testing: Delay Fault Testing of Core-Based Systems-on-a-Chi (QX, NN), pp. 10744–10752.
DATE-2003-JiangMB #algebra #multi: Reducing Multi-Valued Algebraic Operations to Binary (JHRJ, AM, RKB), pp. 10752–10757.
DATE-2003-EbendtGD #bound: Combination of Lower Bounds in Exact BDD Minimization (RE, WG, RD), pp. 10758–10763.
DATE-2003-FreitasO #equation #estimation: Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation (ATF, ALO), pp. 10764–10769.
DATE-2003-SeidlEJ #using: Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information (US, KE, FMJ), pp. 10770–10777.
DATE-2003-AgarwalRV #architecture #pipes and filters: Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology (AA, KR, TNV), pp. 10778–10783.
DATE-2003-SurendraBN #network #reuse: Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation (GS, SB, SKN), pp. 10784–10789.
DATE-2003-DumitrasM #communication #probability: On-Chip Stochastic Communication (TD, RM), pp. 10790–10795.
DATE-2003-MemikKCK #approach #behaviour: An Integrated Approach for Improving Cache Behavior (GM, MTK, ANC, IK), pp. 10796–10801.
DATE-2003-CheungHP #agile #case study: Rapid Configuration and Instruction Selection for an ASIP: A Case Study (NC, JH, SP), pp. 10802–10809.
DATE-2003-Novikov: Local Search for Boolean Relations on the Basis of Unit Propagation (YN), pp. 10810–10815.
DATE-2003-GoelB #analysis #functional #reachability #set: Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis (AG, REB), pp. 10816–10821.
DATE-2003-ShengH #novel #performance #using: Efficient Preimage Computation Using A Novel Success-Driven ATPG (SS, MSH), pp. 10822–10827.
DATE-2003-RoychoudhuryMK #debugging #protocol #using: Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol (AR, TM, SRK), pp. 10828–10833.
DATE-2003-Ziv #functional #metric: Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions (AZ), pp. 10834–10841.
DATE-2003-WittmannHWTS #communication #design #topic: Hot Topic Session: RF Design Technology for Highly Integrated Communication Systems (RW, JH, HJW, GT, MS), pp. 10842–10849.
DATE-2003-WangM #multi #optimisation #using: Power/Ground Mesh Area Optimization Using Multigrid-Based Technique (KW, MMS), pp. 10850–10855.
DATE-2003-LaiYC #evaluation #performance: A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees (STWL, EFYY, CCNC), pp. 10856–10861.
DATE-2003-SmeySM #reduction: Crosstalk Reduction in Area Routing (RMS, BS, PHM), pp. 10862–10867.
DATE-2003-ChenKRZZ #generative #reduction: Area Fill Generation With Inherent Data Volume Reduction (YC, ABK, GR, AZ, YZ), pp. 10868–10875.
DATE-2003-SchlebuschSSGMLGSK #design #problem #question #transaction: Transaction Based Design: Another Buzzword or the Solution to a Design Problem? (HJS, GS, DS, DG, CM, CKL, FG, SS, JK), pp. 10876–10879.
DATE-2003-ZhangM #implementation #independence #satisfiability #using #validation: Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications (LZ, SM), pp. 10880–10885.
DATE-2003-GoldbergN #proving #satisfiability #verification: Verification of Proofs of Unsatisfiability for CNF Formulas (EIG, YN), pp. 10886–10891.
DATE-2003-LuWCH #correlation #learning #satisfiability: A Circuit SAT Solver With Signal Correlation Guided Learning (FL, LCW, KTC, RCYH), pp. 10892–10897.
DATE-2003-CabodiNQ #approximate #bound #model checking #satisfiability #traversal: Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals (GC, SN, SQ), pp. 10898–10905.
DATE-2003-LuzKKS #behaviour #data transformation: Generalized Data Transformations for Enhancing Cache Behavior (VDLL, MTK, IK, US), pp. 10906–10911.
DATE-2003-KuacharoenMM #streaming: Software Streaming via Block Streaming (PK, VJM, VKM), pp. 10912–10917.
DATE-2003-ZhangC #adaptation #embedded #energy #realtime: Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems (YZ, KC), pp. 10918–10925.
DATE-2003-MadalinskiBKY #design #visualisation: Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design (AM, AVB, VK, AY), pp. 10926–10931.
DATE-2003-SokolovBY #optimisation: STG Optimisation in the Direct Mapping of Asynchronous Circuits (DS, AVB, AY), pp. 10932–10939.
DATE-2003-IndrusiakLRG #configuration management #hardware #implementation #ubiquitous: Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues (LSI, FL, RAdLR, MG), pp. 10940–10945.
DATE-2003-MuellerSEW #integration #network #tool support: Dynamic Tool Integration in Heterogeneous Computer Networks (WM, TS, HJE, JW), pp. 10946–10953.
DATE-2003-CassidyPT #concurrent #design #multi #performance #thread: Layered, Multi-Threaded, High-Level Performance Design (ASC, JMP, DET), pp. 10954–10959.
DATE-2003-SchmitzAE #co-evolution #design #embedded #energy #execution #multi: A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities (MTS, BMAH, PE), pp. 10960–10965.
DATE-2003-BraunWSLMN #abstraction #memory management #multi: Processor/Memory Co-Exploration on Multiple Abstraction Levels (GB, AW, OS, RL, HM, AN), pp. 10966–10973.
DATE-2003-GericotaASF #configuration management #logic #runtime: Run-Time Management of Logic Resources on Reconfigurable Systems (MGG, GRA, MLS, JMF), pp. 10974–10979.
DATE-2003-Dales #configuration management: Managing a Reconfigurable Processor in a General Purpose Workstation Environment (MD), pp. 10980–10985.
DATE-2003-MignoletNCVVL #configuration management #design #framework: Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip (JYM, VN, PC, DV, SV, RL), pp. 10986–10993.
DATE-2003-SantosFTT #generative #quality: RTL Test Pattern Generation for High Quality Loosely Deterministic BIST (MBS, JMF, ICT, JPT), pp. 10994–10999.
DATE-2003-PomeranzR #approach #generative #testing: A New Approach to Test Generation and Test Compaction for Scan Circuits (IP, SMR), pp. 11000–11005.
DATE-2003-CornoCRS #automation #generative: Fully Automatic Test Program Generation for Microprocessor Cores (FC, GC, MSR, GS), pp. 11006–11011.
DATE-2003-PomeranzRK #detection #fault #on the: On the Characterization of Hard-to-Detect Bridging Faults (IP, SMR, SK), pp. 11012–11019.
DATE-2003-LeeC #3d #grid #linear #power management #simulation: The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method (YML, CCPC), pp. 11020–11025.
DATE-2003-WangZ #analysis #polynomial: Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching (ZW, JZ), pp. 11026–11031.
DATE-2003-RenczSP #algorithm #layout #performance #simulation: A Fast Algorithm for the Layout Based Electro-Thermal Simulation (MR, VS, AP), pp. 11032–11037.
DATE-2003-HenftlingZBEZ #generative #platform: Platform-Based Testbench Generation (RH, AZ, MB, WE, MZ), pp. 11038–11045.
DATE-2003-TanRJ #approach #architecture #embedded #energy: Software Architectural Transformations: A New Approach to Low Energy Embedded Software (TKT, AR, NKJ), pp. 11046–11051.
DATE-2003-HagaRBM #functional #power management: Dynamic Functional Unit Assignment for Low Power (SH, NR, RB, DM), pp. 11052–11057.
DATE-2003-KandemirKZ #energy #evaluation #implementation #on-demand: Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy (MTK, IK, WZ), pp. 11058–11063.
DATE-2003-NicolaescuVN #embedded #power management: Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors (DN, AVV, AN), pp. 11064–11069.
DATE-2003-BrockmeyerMCC #energy #memory management #multi: Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations (EB, MM, HC, FC), pp. 11070–11075.
DATE-2003-HettiaratchiC #approach #clustering #energy #layout #performance: Mesh Partitioning Approach to Energy Efficient Data Layout (SH, PYKC), pp. 11076–11081.
DATE-2003-MamidipakaD #architecture #embedded #memory management #power management #stack: On-chip Stack Based Memory Organization for Low Power Embedded Architectures (MM, NDD), pp. 11082–11089.
DATE-2003-VogelsG: Figure of Merit Based Selection of A/D Converters (MV, GGEG), pp. 11090–11091.
DATE-2003-KrausP #flexibility #named #synthesis: XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines (OK, MP), pp. 11092–11093.
DATE-2003-KinP #data flow #parallel #simulation #thread: Multithreaded Synchronous Data Flow Simulation (JSK, JLP), pp. 11094–11095.
DATE-2003-FazelTR #design #logic #named #visualisation: PLFire: A Visualization Tool for Asynchronous Phased Logic Designs (KF, MAT, RBR), pp. 11096–11097.
DATE-2003-DoboliGD #clustering #modelling #network #using: Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering (SD, GG, AD), pp. 11098–11099.
DATE-2003-DebOJ #analysis #embedded #simulation #using: Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology (AKD, JÖ, AJ), pp. 11100–11101.
DATE-2003-LoKWH #design #identification #standard: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs (JYLL, WAK, ACHW, TH), pp. 11102–11103.
DATE-2003-ChoiB #migration #network #using: Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration (WC, KB), pp. 11104–11105.
DATE-2003-GirardiB #automation #generative #layout #named: LIT — An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks (AG, SB), pp. 11106–11107.
DATE-2003-MantheLSM #analysis: Symbolic Analysis of Nonlinear Analog Circuits (AM, ZL, CJRS, KM), pp. 11108–11109.
DATE-2003-GerlingSSMT #multi #simulation: Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects (JG, OS, JS, GM, JT), pp. 11110–11111.
DATE-2003-ChoiR #logic: A New Crosstalk Noise Model for DOMINO Logic Circuits (SHC, KR), pp. 11112–11113.
DATE-2003-DingM #logic #modelling: Modeling Noise Transfer Characteristic of Dynamic Logic Gates (LD, PM), pp. 11114–11117.
DATE-2003-KoorapatyCTPPS #architecture #logic #programmable: Heterogeneous Programmable Logic Block Architectures (AK, VC, KYT, CP, LTP, HS), pp. 11118–11119.
DATE-2003-BeckerTVB #architecture #configuration management #industrial #integration: An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration (JB, AT, MV, VB), pp. 11120–11121.
DATE-2003-MoraesMPMC #configuration management #development: Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs (FGM, DM, JCSP, LM, NLVC), pp. 11122–11123.
DATE-2003-RosienGSK: Mapping Applications to an FPFA Tile (MAJR, YG, GJMS, TK), pp. 11124–11125.
DATE-2003-NilssonMOJ #network #proximity: Load Distribution with the Proximity Congestion Awareness in a Network on Chip (EN, MM, JÖ, AJ), pp. 11126–11127.
DATE-2003-AndriahantenainaG #implementation #network: Micro-Network for SoC: Implementation of a 32-Port SPIN network (AA, AG), pp. 11128–11129.
DATE-2003-RettbergZBL #architecture #embedded #pipes and filters #self: A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems (AR, MCZ, CB, TL), pp. 11130–11131.
DATE-2003-BrandoleseFSS #analysis #library: Library Functions Timing Characterization for Source-Level Analysis (CB, WF, FS, DS), pp. 11132–11133.
DATE-2003-ChangKWH #named: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer (ACYC, WAK, ACHW, TH), pp. 11134–11135.
DATE-2003-NielsenM #synthesis: Power Constrained High-Level Synthesis of Battery Powered Digital Systems (SFN, JM), pp. 11136–11137.
DATE-2003-AkgulM #generative #named: PARLAK: Parametrized Lock Cache Generator (BSA, VJMI), pp. 11138–11139.
DATE-2003-KazmierskiY #design #framework: A Secure Web-Based Framework for Electronic System Level Design (TJK, XQY), pp. 11140–11143.
DATE-2003-BeeckGBMCD #data transformation #implementation #power management #realtime: Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor (POdB, CG, EB, MM, FC, GD), pp. 11144–11145.
DATE-2003-ZhangKVID #compilation #energy: Compiler Support for Reducing Leakage Energy Consumption (WZ, MTK, NV, MJI, VD), pp. 11146–11147.
DATE-2003-RongP #capacity #predict: An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries (PR, MP), pp. 11148–11149.
DATE-2003-LuoPJ #communication #distributed #embedded #realtime #scalability: Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems (JL, LSP, NKJ), pp. 11150–11151.
DATE-2003-LeeHH #composition #design #finite #power management #state machine: Decomposition of Extended Finite State Machine for Low Power Design (ML, TH, SYH), pp. 11152–11153.
DATE-2003-YevtushenkoVBPS #equation: Equisolvability of Series vs. Controller’s Topology in Synchronous Language Equations (NY, TV, RKB, AP, ALSV), pp. 11154–11155.
DATE-2003-WedlerSK #encoding #induction #using: Using RTL Statespace Information and State Encoding for Induction Based Property Checking (MW, DS, WK), pp. 11156–11157.
DATE-2003-PastorP #concurrent #simulation #traversal #verification: Combining Simulation and Guided Traversal for the Verification of Concurrent Systems (EP, MAP), pp. 11158–11159.
DATE-2003-SirisantanaR #logic #power management: Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies (NS, KR), pp. 11160–11161.
DATE-2003-Tarnick #embedded #self: Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes (ST), pp. 11162–11163.
DATE-2003-DrineasM #concurrent #detection #fault #monitoring: Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees (PD, YM), pp. 11164–11167.
DATE-2003-HaubeltTFM #satisfiability #synthesis: SAT-Based Techniques in System Synthesis (CH, JT, RF, BM), pp. 11168–11169.
DATE-2003-GrimmMHW #refinement: Refinement of Mixed-Signal Systems with SystemC (CG, CM, WH, KW), pp. 11170–11171.
DATE-2003-TalpinGSGD #design: Polychrony for Refinement-Based Design (JPT, PLG, SKS, RKG, FD), pp. 11172–11173.
DATE-2003-ChenHBW #automation #constraints #generative #monitoring #simulation: Automatic Generation of Simulation Monitors from Quantitative Constraint Formula (XC, HH, FB, YW), pp. 11174–11175.
DATE-2003-SchanstraG #ram #test coverage: Consequences of RAM Bitline Twisting for Test Coverage (IS, AJvdG), pp. 11176–11177.
DATE-2003-CorsiMM #approach #classification #pseudo #random testing #testing: An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme (FC, CM, GM), pp. 11178–11179.
DATE-2003-IchiharaI #fault #generative #testing: Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG (HI, TI), pp. 11180–11181.
DATE-2003-Novak #comparison: Comparison of Test Pattern Decompression Techniques (ON), pp. 11182–11183.
DATE-2003-PolianBR #markov #optimisation #pseudo #random: Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST (IP, BB, SMR), pp. 11184–11185.
DATE-2003-PomeranzR03a #dependence #testing: Test Data Compression Based on Output Dependence (IP, SMR), pp. 11186–11187.
DATE-2003-IyengarCSC #approach #optimisation #testing #using: A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization (VI, AC, SS, KC), pp. 11188–11190.
DATE-2003-IwasakiNNNYONTOIE #multi #scalability: Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level (HI, JN, KN, KN, TY, MO, YN, YT, TO, MI, ME), pp. 20002–20007.
DATE-2003-StolbergBFMFMKKP #architecture #manycore #named: HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications (HJS, MB, LF, SM, SF, XM, MBK, HK, PP), pp. 20008–20013.
DATE-2003-LykakisMVNPSKPR #performance #protocol: Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip (GL, NM, KV, NAN, SP, GS, GEK, DNP, DIR), pp. 20014–20019.
DATE-2003-PanatoBR #algorithm: A Low Device Occupation IP to Implement Rijndael Algorithm (AP, MB, RAdLR), pp. 20020–20025.
DATE-2003-CaldariCCCPT #architecture #modelling #transaction #using: Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 (MC, MC, MC, SC, LP, CT), pp. 20026–20031.
DATE-2003-CaldariCCCOPT #analysis: System-Level Power Analysis Methodology Applied to the AMBA AHB Bus (MC, MC, MC, PC, SO, LP, CT), pp. 20032–20039.
DATE-2003-GlaesonP #design: Designing System-Level Software Solutions for Open OS’s on 3g Wireless Handsets (SG, EP), p. 20040.
DATE-2003-BesanaB #automation #case study #code generation #design #framework #hardware #platform: Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study (MB, MB), pp. 20041–20044.
DATE-2003-JersakREBJW #formal method #integration: Formal Methods for Integration of Automotive Software (MJ, KR, RE, JCB, ZYJ, FW), pp. 20045–20050.
DATE-2003-PetrotG #api #implementation #lightweight #multi #thread: Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect (FP, PG), pp. 20051–20056.
DATE-2003-NicolescuV #approach #detection #fault #tool support: Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results (BN, RV), pp. 20057–20063.
DATE-2003-PaulinPB #challenge #framework #network #platform: Network Processing Challenges and an Experimental NPU Platform (PGP, CP, EB), pp. 20064–20069.
DATE-2003-AdriahantenainaCGMZ #named #scalability: SPIN: A Scalable, Packet Switched, On-Chip Micro-Network (AA, HC, AG, LM, CAZ), pp. 20070–20073.
DATE-2003-SoniRHRV #named #network #performance: NPSE: A High Performance Network Packet Search Engine (NS, NR, LBH, SR, GV), pp. 20074–20081.
DATE-2003-AraS #component #transaction #verification: A Proposal for Transaction-Level Verification with Component Wrapper Language (KA, KS), pp. 20082–20087.
DATE-2003-CarbognaniLICB #modelling #precise #standard #using #verification: Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard (FC, CKL, CNI, AC, PB), pp. 20088–20094.
DATE-2003-SayintaCPAD #abstraction #case study #using #verification: A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification (AS, GC, MP, AA, WD), pp. 20095–20100.
DATE-2003-BombanaB #synthesis: SystemC-VHDL Co-Simulation and Synthesis in the HW Domain (MB, FB), pp. 20101–20105.
DATE-2003-CoppolaCGM #communication #named #refinement: IPSIM: SystemC 3.0 Enhancements for Communication Refinement (MC, SC, MDG, GM), pp. 20106–20111.
DATE-2003-BruschiF #behaviour #modelling #synthesis: Synthesis of Complex Control Structures from Behavioral SystemC Models (FB, FF), pp. 20112–20119.
DATE-2003-MoussaGN #modelling #performance #transaction #using: Exploring SW Performance Using SoC Transaction-Level Modeling (IM, TG, GN), pp. 20120–20125.
DATE-2003-Goltze #architecture #communication #flexibility #object-oriented: A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices (MG), pp. 20126–20131.
DATE-2003-ChoLYCZ #analysis #communication #design #scheduling: Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design (YC, GL, SY, KC, NEZ), pp. 20132–20137.
DATE-2003-HondaT #design #evaluation: Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device (SH, HT), pp. 20138–20143.
DATE-2003-DuSTBAF #configuration management #interactive: Interactive Ray Tracing on Reconfigurable SIMD MorphoSys (HD, MSE, NT, NB, MLA, MF), pp. 20144–20149.
DATE-2003-JanDE #case study #development #embedded #encryption #migration #network: Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development (SJ, PdD, SAE), pp. 20150–20157.
DATE-2003-LiliusTV #architecture #evaluation #performance #protocol: Fast Evaluation of Protocol Processor Architectures for IPv6 Routing (JL, DT, SV), pp. 20158–20163.
DATE-2003-BriniBC #architecture #communication #flexibility #framework #platform: A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems (SB, DB, FC), pp. 20164–20169.
DATE-2003-KodaseWS #constraints #embedded #realtime #runtime: Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints (SK, SW, KGS), pp. 20170–20175.
DATE-2003-OgawaNCSWNST #approach #architecture #optimisation #transaction: A Practical Approach for Bus Architecture Optimization at Transaction Level (OO, SBdN, PC, KS, YW, HN, TS, YT), pp. 20176–20181.
DATE-2003-PalermoSZ #architecture #embedded: Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture (GP, CS, VZ), pp. 20182–20187.
DATE-2003-DragoFMPP #architecture #embedded #estimation #performance #tuple: Estimation of Bus Performance for a Tuplespace in an Embedded Architecture (ND, FF, MM, GP, MP), pp. 20188–20195.
DATE-2003-BurmenPT #cost analysis #design #optimisation #robust: Defining Cost Functions for Robust IC Design and Optimization (ÁB, JP, TT), pp. 20196–20201.
DATE-2003-SchraderM #design: SoC Design and Test Considerations (MS, RM), pp. 20202–20207.
DATE-2003-LaurentK #validation: A System to Validate and Certify Soft and Hard IP (BL, TK), pp. 20208–20213.
DATE-2003-CaldariCCMGOT #modelling: SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel (MC, MC, PC, GM, FDG, SO, CT), pp. 20214–20219.
DATE-2003-RemondB #design #set: Set Top Box SoC Design Methodology at STMicroelectronics (FR, PB), pp. 20220–20223.
DATE-2003-AndritsopoulosCDKMPTPR #case study #verification: Verification of a Complex SoC: The PRO3 Case-Study (FA, CC, GD, FK, YM, FP, IT, SP, DIR), pp. 20224–20231.
DATE-2003-MangerucaFSPP #case study #design #detection #embedded: System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain (LM, AF, ALSV, AP, MP), pp. 20232–20237.
DATE-2003-VerderberZL #implementation #optimisation #video: HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder (MV, AZ, DL), pp. 20238–20243.
DATE-2003-HelmschmidtSRRMB #configuration management: Reconfigurable Signal Processing in Wireless Terminals (JH, ES, PR, SR, SdM, RB), pp. 20244–20249.
DATE-2003-BaganneBEGM #case study #design #integration #multi: A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration (AB, IB, ME, RG, EM), pp. 20250–20255.
DATE-2003-GriesKSK #case study #modelling #network #simulation: Comparing Analytical Modeling with Simulation for Network Processors: A Case Study (MG, CK, CS, KK), pp. 20256–20261.
DATE-2003-Pirola #hardware #memory management: A Solution for Hardware Emulation of Non Volatile Memory Macrocells (AP), pp. 20262–20267.
DATE-2003-AholaWS #design: Bluetooth Transceiver Design with VHDL-AMS (RA, DW, MS), pp. 20268–20273.
DATE-2003-DaglioR #bottom-up #design #top-down: A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies (PD, CR), pp. 20274–20279.
DATE-2003-MounirMF #automation #behaviour #performance #verification: Automatic Behavioural Model Calibration for Efficient PLL System Verification (AM, AM, MF), pp. 20280–20285.
DATE-2003-KnochelMHKA #simulation #verification: Verification of the RF Subsystem within Wireless LAN System Level Simulation (UK, TM, JH, RK, RA), pp. 20286–20291.
DATE-2003-McCorquodaleGKMSB #challenge #design #top-down: A Top-Down Microsystems Design Methodology and Associated Challenges (MSM, FHG, KLK, EDM, RMS, RBB), pp. 20292–20296.
DATE-2003-IskanderDAMHSM #synthesis #using: Synthesis of CMOS Analog Cells Using AMIGO (RI, MD, MA, MM, NH, NS, SM), pp. 20297–20302.

Proceedings of the Eighth Conference on Design, Automation and Test in EuropeDATE, 2003.

Contents (267 items)

Proceedings of the Eighth Conference on Design, Automation and Test in Europe
DATE, 2003.