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Collaborated with:
A.Reid R.Chen D.Gilday D.Hoyes W.Keen A.Pathirane O.Shepherd P.Vrabel A.Zaidi
Talks about:
end (2) processor (1) formal (1) verif (1) isa (1)

Person: Anastasios Deligiannis

DBLP DBLP: Deligiannis:Anastasios

Contributed to:

CAV (2) 20162016

Wrote 1 papers:

CAV-2016-ReidCDGHKPSVZ #verification
End-to-End Verification of Processors with ISA-Formal (AR, RC, AD, DG, DH, WK, AP, OS, PV, AZ), pp. 42–58.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.