Travelled to:1 × France
1 × Germany
1 × The Netherlands
2 × USA
Collaborated with:∅ B.Boissinot F.Rastello D.v.Amstel M.Poulhiès G.Lager A.Darte C.Guillon S.Hack D.Grund
Talks about:ssa (3) form (2) code (2) processor (1) translat (1) parallel (1) schedul (1) revisit (1) qualiti (1) program (1)
Person: Benoît Dupont de Dinechin
DBLP: Dinechin:Beno=icirc=t_Dupont_de
Contributed to:
2014
2014
200920081999Wrote 5 papers:
- CC-2014-Dinechin #code generation #using
- Using the SSA-Form in a Code Generator (BDdD), pp. 1–17.
- DATE-2014-DinechinAPL #parallel
- Time-critical computing on a single-chip massively parallel processor (BDdD, DvA, MP, GL), pp. 1–6.
- CGO-2009-BoissinotDRDG #correctness #performance #quality
- Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency (BB, AD, FR, BDdD, CG), pp. 114–125.
- CGO-2008-BoissinotHGDR #liveness #performance #source code
- Fast liveness checking for ssa-form programs (BB, SH, DG, BDdD, FR), pp. 35–44.
- CC-1999-Dinechin #memory management #scheduling
- Extending Modulo Scheduling with Memory Reference Merging (BDdD), pp. 274–287.