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Travelled to:
1 × USA
Collaborated with:
K.Chakraborty S.Roy D.M.Ancajas
Talks about:
microprocessor (1) pipelin (1) violat (1) effici (1) toler (1) time (1)

Person: Brennan Cozzens

DBLP DBLP: Cozzens:Brennan

Contributed to:

DAC 20132013

Wrote 1 papers:

DAC-2013-ChakrabortyCRA #pipes and filters
Efficiently tolerating timing violations in pipelined microprocessors (KC, BC, SR, DMA), p. 8.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.