BibSLEIGH — Proceedings of the 50th Annual Design Automation Conference

Proceedings of the 50th Annual Design Automation Conference
DAC, 2013.

SYS

@proceedings{DAC-2013,
	acmid         = "2463209",
	address       = "Austin, Texas, USA",
	isbn          = "978-1-4503-2071-9",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 50th Annual Design Automation Conference}",
	year          = 2013,
}

Contents (185 items)

DAC-2013-GeierBYDSGC #exclamation: Let’s put the car in your phone! (MG, MB, DY, BD, RS, DG, SC), p. 2.
DAC-2013-Ghosh #memory management: Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power (SG), p. 2.
DAC-2013-KrishnaswamyBP #question: Can CAD cure cancer? (SK, BB, DP), p. 2.
DAC-2013-WeiP #detection #hardware: The undetectable and unprovable hardware trojan horse (SW, MP), p. 2.
DAC-2013-GoncalvesPPD: Non-volatile FPGAs based on spintronic devices (OG, GP, GdP, BD), p. 3.
DAC-2013-KarnikPB #delivery #power management: Power management and delivery for high-performance microprocessors (TK, M(P, SB), p. 3.
DAC-2013-SekitaniYTSS #using: Electrical artificial skin using ultraflexible organic transistor (TS, TY, MT, TS, TS), p. 3.
DAC-2013-ShulakerRHCGWM #named: Sacha: the Stanford carbon nanotube controlled handshaking robot (MMS, JVR, GH, HYC, GGEG, HSPW, SM), p. 3.
DAC-2013-CharbonR #image: Single-photon image sensors (EC, FR), p. 4.
DAC-2013-CorbalanKTLRN #3d #challenge: Power and signal integrity challenges in 3D systems (MC, AK, TT, DL, RR, MN), p. 4.
DAC-2013-FariborziCNCHLLS: Relays do not leak: CMOS does (HF, FC, RN, IRC, LH, RL, TJKL, VS), p. 4.
DAC-2013-GaillardonMABSLM #towards #using: Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
DAC-2013-Flynn #power management: Power gating applied to MP-SoCs for standby-mode power management (DF), p. 5.
DAC-2013-YousofshahiOLH #capacity #identification #nondeterminism: Gene modification identification under flux capacity uncertainty (MY, MO, KL, SH), p. 5.
DAC-2013-AgostaBMP #analysis: Compiler-based side channel vulnerability analysis and optimized countermeasures application (GA, AB, MM, GP), p. 6.
DAC-2013-AlaghiLH #probability #realtime: Stochastic circuits for real-time image-processing applications (AA, CL, JPH), p. 6.
DAC-2013-AmaruGM #composition #logic #named #synthesis: BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition (LGA, PEG, GDM), p. 6.
DAC-2013-AnagnostopoulosTBS #distributed #manycore #platform #resource management #runtime: Distributed run-time resource management for malleable applications on many-core platforms (IA, VT, AB, DS), p. 6.
DAC-2013-AsenovART #performance #predict: Predicting future technology performance (AA, CA, CR, ET), p. 6.
DAC-2013-CalhounC #delivery #energy #flexibility #performance #power management: Flexible on-chip power delivery for energy efficient heterogeneous systems (BHC, KC), p. 6.
DAC-2013-CalimeraMP #constraints #energy #fault #scheduling: Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints (AC, EM, MP), p. 6.
DAC-2013-ChandrikakuttyUTW #hardware #monitoring #network: High-performance hardware monitors to protect network processors from data plane attacks (HC, DU, RT, TW), p. 6.
DAC-2013-ChenWBA #random #reuse #simulation #verification: Simulation knowledge extraction and reuse in constrained random processor verification (WC, LCW, JB, MSA), p. 6.
DAC-2013-ChienOCKC: Double patterning lithography-aware analog placement (HCCC, HCO, TCC, TYK, YWC), p. 6.
DAC-2013-DallyMK #design #tool support: 21st century digital design tools (WJD, CM, SWK), p. 6.
DAC-2013-DevWR #3d #integration #testing #using: High-throughput TSV testing and characterization for 3D integration using thermal mapping (KD, GW, SR), p. 6.
DAC-2013-DinakarraoWY #3d #multi #reduction: Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor (SMPD, KW, HY), p. 6.
DAC-2013-Du0SSLMW #self: Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography (YD, QM, HS, JS, GLP, AM, MDFW), p. 6.
DAC-2013-EbrahimiAT #analysis #approach #multi: A layout-based approach for multiple event transient analysis (ME, HA, MBT), p. 6.
DAC-2013-FangLC #multi: Stitch-aware routing for multiple e-beam lithography (SYF, IJL, YWC), p. 6.
DAC-2013-FanRRV #design #encryption #energy #security: Low-energy encryption for medical devices: security adds an extra design dimension (JF, OR, VR, IV), p. 6.
DAC-2013-FattahDLP #agile #manycore: Smart hill climbing for agile dynamic mapping in many-core systems (MF, MD, PL, JP), p. 6.
DAC-2013-HeHCKLCY #integration #quality: Ripple 2.0: high quality routability-driven placement via global router integration (XH, TH, WKC, JK, KCL, WC, EFYY), p. 6.
DAC-2013-HoC #multi: Multiple chip planning for chip-interposer codesign (YKH, YWC), p. 6.
DAC-2013-HoOCT #array: Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits (KHH, HCO, YWC, HFT), p. 6.
DAC-2013-HsuCHCC #design: Routability-driven placement for hierarchical mixed-size circuit designs (MKH, YFC, CCH, TCC, YWC), p. 6.
DAC-2013-JiangYXCE #3d #effectiveness #on the #performance: On effective and efficient in-field TSV repair for stacked 3D ICs (LJ, FY, QX, KC, BE), p. 6.
DAC-2013-Kahng #design #process #roadmap: The ITRS design technology and system drivers roadmap: process and status (ABK), p. 6.
DAC-2013-KarakostasTUNC #energy #performance: Improving the energy efficiency of hardware-assisted watchpoint systems (VK, ST, OSÜ, MN, AC), p. 6.
DAC-2013-KimJK #algorithm #problem: An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem (JK, DJ, TK), p. 6.
DAC-2013-KinsmanKN #generative #sequence #validation: Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation (ABK, HFK, NN), p. 6.
DAC-2013-KleebergerGS #evaluation #modelling #performance #predict #standard: Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies (VK, HEG, US), p. 6.
DAC-2013-KuangY #approach #composition #layout #performance: An efficient layout decomposition approach for triple patterning lithography (JK, EFYY), p. 6.
DAC-2013-KunduCSK: An ATE assisted DFD technique for volume diagnosis of scan chains (SK, SC, IS, RK), p. 6.
DAC-2013-LeeH #mobile: An optimized page translation for mobile virtualization (YCL, CwH), p. 6.
DAC-2013-LeGHD #simulation #using #verification: Verifying SystemC using an intermediate verification language and symbolic simulation (HML, DG, VH, RD), p. 6.
DAC-2013-LeiXC #consistency #prototype: Post-silicon conformance checking with virtual prototypes (LL, FX, KC), p. 6.
DAC-2013-LinBC #effectiveness #performance: An efficient and effective analytical placer for FPGAs (THL, PB, YWC), p. 6.
DAC-2013-LinCLWC #detection #fuzzy #novel: A novel fuzzy matching model for lithography hotspot detection (SYL, JYC, JCL, WYW, SCC), p. 6.
DAC-2013-LinLM #analysis #hybrid #kernel #reachability #verification: Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis (HL, PL, CJM), p. 6.
DAC-2013-LiuHLMCHZ: Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine (BL, MH, HL, ZHM, YC, TH, WZ), p. 6.
DAC-2013-LiuYLC #named #using: DuraCache: a durable SSD cache using MLC NAND flash (RSL, CLY, CHL, GYC), p. 6.
DAC-2013-LukasiewyczSASWCKMSFC #architecture #design: System architecture and software design for electric vehicles (ML, SS, SA, FS, PW, WC, MK, PM, SS, SAF, SC), p. 6.
DAC-2013-LuYHF0 #named: RISO: relaxed network-on-chip isolation for cloud processors (HL, GY, YH, BF, XL), p. 6.
DAC-2013-MallikZLCBBBCRBMV #analysis #evaluation #framework #named: TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes (AM, PZ, TTL, BC, BB, PRDB, RB, KC, JR, MB, AM, DV), p. 6.
DAC-2013-MercatiBPRB #manycore #reliability #user interface: Workload and user experience-aware dynamic reliability management in multicore processors (PM, AB, FP, TSR, LB), p. 6.
DAC-2013-MillerVG #modelling #physics #statistics #using: Exploration with upgradeable models using statistical methods for physical model emulation (BM, FV, TG), p. 6.
DAC-2013-MishraS #grid #power management: The impact of electromigration in copper interconnects on power grid integrity (VM, SSS), p. 6.
DAC-2013-Miskov-ZivanovMF #analysis #automation #behaviour #design #network: Dynamic behavior of cell signaling networks: model design and analysis automation (NMZ, DM, JRF), p. 6.
DAC-2013-NacciRBSBA #algorithm #implementation #synthesis: A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices (AAN, VR, FB, DS, IB, DA), p. 6.
DAC-2013-NajjarV #compilation #perspective: FPGA code accelerators — the compiler perspective (WAN, JRV), p. 6.
DAC-2013-NathAR #concurrent #scheduling #thread: Temperature aware thread block scheduling in GPGPUs (RN, RZA, TSR), p. 6.
DAC-2013-OnizawaG #clustering #network #power management #scalability: Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks (NO, WJG), p. 6.
DAC-2013-OuCC: Simultaneous analog placement and routing with current flow and current density considerations (HCO, HCCC, YWC), p. 6.
DAC-2013-ParkKC #energy #hybrid: Hybrid energy storage systems and battery management for electric vehicles (SP, YK, NC), p. 6.
DAC-2013-ParkZDK #recognition: Accelerators for biologically-inspired attention and recognition (MSP, CZ, MD, SK), p. 6.
DAC-2013-QuanP #algorithm #runtime: A scenario-based run-time task mapping algorithm for MPSoCs (WQ, ADP), p. 6.
DAC-2013-RahimiBG #architecture: Aging-aware compiler-directed VLIW assignment for GPGPU architectures (AR, LB, RKG), p. 6.
DAC-2013-RamasubramanianVPR #design #energy #named: Relax-and-retime: a methodology for energy-efficient recovery based design (SGR, SV, AP, AR), p. 6.
DAC-2013-RellermeyerLK #embedded #operating system #platform: Cloud platforms and embedded computing: the operating systems of the future (JSR, SWL, MK), p. 6.
DAC-2013-RostamiBKJ #question #security: Balancing security and utility in medical devices? (MR, WB, FK, AJ), p. 6.
DAC-2013-SalodkarRBB #automation #design #multi: Automatic design rule correction in presence of multiple grids and track patterns (NS, SR, SB, SHB), p. 6.
DAC-2013-ShafaeiSP #architecture #distance #interactive #linear #nearest neighbour #optimisation #quantum: Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures (AS, MS, MP), p. 6.
DAC-2013-SharadFR #memory management #power management: Ultra low power associative computing with spin neurons and resistive crossbar memory (MS, DF, KR), p. 6.
DAC-2013-SunWL #design #memory management #power management: Cross-layer racetrack memory design for ultra high density and low power consumption (ZS, WW, HHL), p. 6.
DAC-2013-TrivediCM #case study #power management: Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier (ART, SC, SM), p. 6.
DAC-2013-TsaoCY #design #garbage collection #performance: Performance enhancement of garbage collection for flash storage devices: an efficient victim block selection design (CWT, YHC, MCY), p. 6.
DAC-2013-TsengGS #power management: Underpowering NAND flash: profits and perils (HWT, LMG, SS), p. 6.
DAC-2013-TuJ #feedback #synthesis: Synthesis of feedback decoders for initialized encoders (KHT, JHRJ), p. 6.
DAC-2013-WagstaffGFT #architecture #partial evaluation #set: Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description (HW, MG, BF, NPT), p. 6.
DAC-2013-WangZSLG #modelling #performance #reuse #scalability: Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data (FW, WZ, SS, XL, CG), p. 6.
DAC-2013-WuWLH #algorithm #generative #model checking #satisfiability: A counterexample-guided interpolant generation algorithm for SAT-based model checking (CYW, CAW, CYL, CY(H), p. 6.
DAC-2013-XiongW #abstraction #constraints #grid #power management #verification: Constraint abstraction for vectorless power grid verification (XX, JW), p. 6.
DAC-2013-XuNMJX #comprehension #design #memory management #multi #trade-off: Understanding the trade-offs in multi-level cell ReRAM memory design (CX, DN, NM, NPJ, YX), p. 6.
DAC-2013-XuWHRT #estimation #on the #performance #robust: On robust task-accurate performance estimation (YX, BW, RH, RR, JT), p. 6.
DAC-2013-YangCTH #performance: New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices (MCY, YHC, CWT, PCH), p. 6.
DAC-2013-YangRHX #behaviour #design #equivalence #implementation #optimisation #synthesis: Handling design and implementation optimizations in equivalence checking for behavioral synthesis (ZY, SR, KH, FX), p. 6.
DAC-2013-YeWHL #parallel #segmentation #simulation: Time-domain segmentation based massively parallel simulation for ADCs (ZY, BW, SH, YL), p. 6.
DAC-2013-YeYSJX #generative: Post-placement voltage island generation for timing-speculative circuits (RY, FY, ZS, WBJ, QX), p. 6.
DAC-2013-YinQ #security: Improving PUF security with regression-based distiller (CEDY, GQ), p. 6.
DAC-2013-YuanLJX #on the #testing: On testing timing-speculative circuits (FY, YL, WBJ, QX), p. 6.
DAC-2013-YuanX #fault #logic #low cost #named #scalability: InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits (FY, QX), p. 6.
DAC-2013-YuLJC #classification #detection #feature model #using: Machine-learning-based hotspot detection using topological classification and critical feature extraction (YTY, GHL, IHRJ, CC), p. 6.
DAC-2013-ZhangLSSR #automation #clustering: Automatic clustering of wafer spatial signatures (WZ, XL, SS, AJS, RAR), p. 6.
DAC-2013-ZhangRJ #network #towards: Towards trustworthy medical devices and body area networks (MZ, AR, NKJ), p. 6.
DAC-2013-ZhanSOTNX #design #embedded #energy #optimisation #realtime: Designing energy-efficient NoC for real-time embedded systems through slack optimization (JZ, NS, JO, LT, VN, YX), p. 6.
DAC-2013-ZhouLJ #3d #complexity #finite #linear #multi #scalability: A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectrics (BZ, HL, DJ), p. 6.
DAC-2013-AxerE #fault #probability #scheduling: Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors (PA, RE), p. 7.
DAC-2013-BanerjeeDSC #adaptation #constraints #energy #performance #realtime: Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints (DB, SKD, SS, AC), p. 7.
DAC-2013-BenazouzKHB #data flow #evaluation #graph #liveness: Liveness evaluation of a cyclo-static DataFlow graph (MB, AMK, TH, BB), p. 7.
DAC-2013-ChenXKGHKOA #design #manycore #scalability: Dynamic voltage and frequency scaling for shared resources in multicore processor designs (XC, ZX, HK, PVG, JH, MK, ÜYO, RZA), p. 7.
DAC-2013-DoustiP #algorithm #estimation #latency #named #quantum: LEQA: latency estimation for a quantum algorithm mapped to a quantum circuit fabric (MJD, MP), p. 7.
DAC-2013-GaribottiOBkASR #distributed #embedded #memory management #multi #thread: Simultaneous multithreading support in embedded distributed memory MPSoCs (RG, LO, RB, Mk, CAJ, GS, MR), p. 7.
DAC-2013-GuCL #estimation #performance #validation: Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation (CG, EC, XL), p. 7.
DAC-2013-HuKM #complexity #coordination: Taming the complexity of coordinated place and route (JH, MCK, ILM), p. 7.
DAC-2013-JangPK #simulation: An event-driven simulation methodology for integrated switching power supplies in SystemVerilog (JEJ, MJP, JK), p. 7.
DAC-2013-KahngKL #reduction: Smart non-default routing for clock power reduction (ABK, SK, HL), p. 7.
DAC-2013-KuruvillaSPVC #analysis #optimisation #set #statistics: Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization (VK, DS, JP, CV, NC), p. 7.
DAC-2013-LiSARHP #adaptation #embedded #fault #named #runtime: RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors (TL, MS, JAA, SR, JH, SP), p. 7.
DAC-2013-LiuC #on the #synthesis: On learning-based methods for design-space exploration with high-level synthesis (HYL, LPC), p. 7.
DAC-2013-LiuCHVNBP #design #energy #logic #physics: Minimum-energy state guided physical design for nanomagnet logic (SL, GC, XSH, EV, MTN, GHB, WP), p. 7.
DAC-2013-LuoCH #design #nondeterminism: Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations (YL, KC, TYH), p. 7.
DAC-2013-SinghDK #energy #execution #multi #optimisation #streaming: Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systems (AKS, AD, AK), p. 7.
DAC-2013-SongLPL #3d #multi #optimisation: Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs (TS, CL, YP, SKL), p. 7.
DAC-2013-StratigopoulosFCM #estimation #metric #multi #statistics #using: Multidimensional analog test metrics estimation using extreme value theory and statistical blockade (HGDS, PF, YC, FM), p. 7.
DAC-2013-TurakhiaRGM #architecture #multi #named #synthesis: HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors (YT, BR, SG, DM), p. 7.
DAC-2013-Wang #fault #reliability: Hierarchical decoding of double error correcting codes for high speed reliable memories (ZW), p. 7.
DAC-2013-WangK #control flow #detection #hardware #kernel #named #performance #using: NumChecker: detecting kernel control-flow modifying rootkits by using hardware performance counters (XW, RK), p. 7.
DAC-2013-WuH #constraints #framework #multi #random #robust #set #theorem proving #verification: A robust constraint solving framework for multiple constraint sets in constrained random verification (BHW, CY(H), p. 7.
DAC-2013-YuYGP #named: E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system (BY, KY, JRG, DZP), p. 7.
DAC-2013-ZhangPFH: Lighting the dark silicon by exploiting heterogeneity on future processors (YZ, LP, XF, YH), p. 7.
DAC-2013-ZhanR #energy: Techniques for energy-efficient power budgeting in data centers (XZ, SR), p. 7.
DAC-2013-0001WAWG #approach #empirical #estimation #towards: Towards variation-aware system-level power estimation of DRAMs: an empirical approach (KC, CW, BA, NW, KG), p. 8.
DAC-2013-AgrawalRHSPC #architecture #clustering #framework #multi #platform: Early exploration for platform architecture instantiation with multi-mode application partitioning (PA, PR, MH, NS, LVdP, FC), p. 8.
DAC-2013-AvinashBEPP #energy #fault #hardware: Improving energy gains of inexact DSP hardware through reciprocative error compensation (LA, AB, CCE, KVP, CP), p. 8.
DAC-2013-CarloYM #3d #delivery #induction #integration #on the #power management: On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery (SC, WY, SM), p. 8.
DAC-2013-ChakrabortyCRA #pipes and filters: Efficiently tolerating timing violations in pipelined microprocessors (KC, BC, SR, DMA), p. 8.
DAC-2013-CongX #fault #programmable: Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance (JC, BX), p. 8.
DAC-2013-Feng #grid #power management #scalability #verification: Scalable vectorless power grid current integrity verification (ZF), p. 8.
DAC-2013-HanZF #gpu #named #parallel #simulation: TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations (LH, XZ, ZF), p. 8.
DAC-2013-JahnPKCH #configuration management #optimisation #pipes and filters: Optimizations for configuring and mapping software pipelines in many core systems (JJ, SP, SK, JJC, JH), p. 8.
DAC-2013-LiaoHL #detection #fault: GPU-based n-detect transition fault ATPG (KYL, SCH, JCML), p. 8.
DAC-2013-LiP #framework #modelling: An accurate semi-analytical framework for full-chip TSV-induced stress modeling (YL, DZP), p. 8.
DAC-2013-LiuWSALLV #constraints #design #estimation: Routing congestion estimation with real design constraints (WHL, YW, CCNS, CJA, ZL, YLL, NV), p. 8.
DAC-2013-LiuYLW #modelling #optimisation: Polyhedral model based mapping optimization of loop nests for CGRAs (DL, SY, LL, SW), p. 8.
DAC-2013-LuBS #data transformation #multi #named #stack: SSDM: smart stack data management for software managed multicores (SMMs) (JL, KB, AS), p. 8.
DAC-2013-MaricAV #adaptation #energy #hybrid #named #predict #reliability: APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation (BM, JA, MV), p. 8.
DAC-2013-RoyCPP #parallel #synthesis #towards #trade-off: Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures (SR, MRC, RP, DZP), p. 8.
DAC-2013-TajikHD #3d #architecture #manycore #named #process: VAWOM: temperature and process variation aware wearout management in 3D multicore architecture (HT, HH, ND), p. 8.
DAC-2013-TangAP #communication #configuration management #multi #pipes and filters: Reconfigurable pipelined coprocessor for multi-mode communication transmission (LT, JAA, SP), p. 8.
DAC-2013-WangLZZC #array #clustering #memory management #multi #synthesis: Memory partitioning for multidimensional arrays in high-level synthesis (YW, PL, PZ, CZ, JC), p. 8.
DAC-2013-ZhaiBS #parallel #realtime #streaming: Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems (JTZ, MB, TS), p. 8.
DAC-2013-ZhangGQ #embedded #energy #performance #scheduling: Improving charging efficiency with workload scheduling in energy harvesting embedded systems (YZ, YG, QQ), p. 8.
DAC-2013-ZhangYWSX #hardware #named #trust #verification: VeriTrust: verification for hardware trust (JZ, FY, LW, ZS, QX), p. 8.
DAC-2013-AncajasCR #3d #manycore #memory management #named: DMR3D: dynamic memory relocation in 3D multicore systems (DMA, KC, SR), p. 9.
DAC-2013-AngioneCCLN #modelling: Pareto epsilon-dominance and identifiable solutions for BioCAD modeling (CA, JC, GC, PL, GN), p. 9.
DAC-2013-BombieriLFC #c++ #synthesis: A method to abstract RTL IP blocks into C++ code and enable high-level synthesis (NB, HYL, FF, LPC), p. 9.
DAC-2013-ChippaCRR #analysis #approximate: Analysis and characterization of inherent application resilience for approximate computing (VKC, STC, KR, AR), p. 9.
DAC-2013-GeorgakosSSC #architecture #challenge #reliability: Reliability challenges for electric vehicles: from devices to architecture and systems software (GG, US, RS, SC), p. 9.
DAC-2013-GoswamiLKSMCR #development #modelling #verification: Model-based development and verification of control software for electric vehicles (DG, ML, MK, SS, AM, SC, SR), p. 9.
DAC-2013-GrissomB #programmable: A field-programmable pin-constrained digital microfluidic biochip (DG, PB), p. 9.
DAC-2013-GrossmanTBS #design #framework #simulation: The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputers (JPG, BT, JAB, DES), p. 9.
DAC-2013-KarthikR #approximate #linear #modelling #named #using: ABCD-L: approximating continuous linear systems using boolean models (KVA, JSR), p. 9.
DAC-2013-LiuKL #optimisation: Optimization of placement solutions for routability (WHL, CKK, YLL), p. 9.
DAC-2013-MuthukaruppanPVMV #manycore #power management #symmetry: Hierarchical power management for asymmetric multi-core in dark silicon era (TSM, MP, VV, TM, SV), p. 9.
DAC-2013-ShafiqueRAH #fault #optimisation #reliability: Exploiting program-level masking and error propagation for constrained reliability optimization (MS, SR, PVA, JH), p. 9.
DAC-2013-WangW #named: SAW: system-assisted wear leveling on the write endurance of NAND flash devices (CW, WFW), p. 9.
DAC-2013-WangYRNZMMB #design #grid #power management: Role of power grid in side channel attack and power-grid-aware secure design (XW, WY, DBR, SN, YZ, SM, DM, SB), p. 9.
DAC-2013-WuergesOS #energy #performance #realtime: Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching (EW, RSdO, LCVdS), p. 9.
DAC-2013-ZhengHB #array #embedded #named #physics #robust: RESP: a robust physical unclonable function retrofitted into embedded SRAM array (YZ, MH, SB), p. 9.
DAC-2013-AbousamraJM #multi: Proactive circuit allocation in multiplane NoCs (AA, AKJ, RGM), p. 10.
DAC-2013-AlleMD #analysis #dependence #pipes and filters #runtime #synthesis: Runtime dependency analysis for loop pipelining in high-level synthesis (MA, AM, SD), p. 10.
DAC-2013-AncajasNCR #architecture: HCI-tolerant NoC router microarchitecture (DMA, JMN, KC, SR), p. 10.
DAC-2013-AndalamGSRR #analysis #precise: Precise timing analysis for direct-mapped caches (SA, AG, RS, PSR, JR), p. 10.
DAC-2013-BartoliniCDMSS #operating system #research: The autonomic operating system research project: achievements and future directions (DBB, RC, GD, MM, MDS, FS), p. 10.
DAC-2013-ChakrabortyLAP #physics: A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique (RC, CL, DA, JP), p. 10.
DAC-2013-ChoMCAM #design #evaluation #fault #injection #robust: Quantitative evaluation of soft error injection techniques for robust system design (HC, SM, CYC, JAA, SM), p. 10.
DAC-2013-ColmenaresEHBMCGRBMAK #adaptation #named #refactoring: Tessellation: refactoring the OS around explicit resource containers with continuous adaptation (JAC, GE, SAH, SB, MM, DC, BG, ER, DBB, NM, KA, JK), p. 10.
DAC-2013-DingLM #analysis #multi #realtime: Integrated instruction cache analysis and locking in multitasking real-time systems (HD, YL, TM), p. 10.
DAC-2013-Fang #simulation: A new time-stepping method for circuit simulation (GPF), p. 10.
DAC-2013-GirbalMGAQCY #convergence #on the: On the convergence of mainstream and mission-critical markets (SG, MM, AG, JA, EQ, FJC, SY), p. 10.
DAC-2013-HamzehSV #architecture #configuration management #named: REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs) (MH, AS, SBKV), p. 10.
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap: Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DAC-2013-HillsZMSWWM #agile #design #guidelines: Rapid exploration of processing and design guidelines to overcome carbon nanotube variations (GH, JZ, CM, MMS, HW, HSPW, SM), p. 10.
DAC-2013-JungPPC #distributed #embedded #framework #named #platform #scalability: netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems (YJ, JP, MP, LPC), p. 10.
DAC-2013-KauerNSLCH #architecture #composition #concurrent: Modular system-level architecture for concurrent cell balancing (MK, SN, SS, ML, SC, LH), p. 10.
DAC-2013-KimOCHH #distributed #embedded #estimation #novel: A novel analytical method for worst case response time estimation of distributed embedded systems (JK, HO, JC, HH, SH), p. 10.
DAC-2013-LeeLL #3d: Power benefit study for ultra-high density transistor-level monolithic 3D ICs (YJL, DBL, SKL), p. 10.
DAC-2013-MinJP #energy #named #optimisation #reduction: XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs (SMM, HJ, SP), p. 10.
DAC-2013-MishraMD #approach #design #multi: A heterogeneous multiple network-on-chip design: an application-aware approach (AKM, OM, CRD), p. 10.
DAC-2013-PapakonstantinouCHCL #kernel #migration: Throughput-oriented kernel porting onto FPGAs (AP, DC, WmWH, JC, YL), p. 10.
DAC-2013-RaiSST #algorithm #analysis #distributed #network #process: Distributed stable states for process networks: algorithm, analysis, and experiments on intel SCC (DR, LS, NS, LT), p. 10.
DAC-2013-ShahzadKRPC #algorithm #encryption #named: CoARX: a coprocessor for ARX-based cryptographic algorithms (KS, AK, ZER, GP, AC), p. 10.
DAC-2013-SinghSKH #manycore #overview #roadmap: Mapping on multi/many-core systems: survey of current and emerging trends (AKS, MS, AK, JH), p. 10.
DAC-2013-SchurmansZALACW #architecture #automation #communication #modelling #using: Creation of ESL power models for communication architectures using automatic calibration (SS, DZ, DA, RL, GA, XC, LW), p. 58.

Proceedings of the 50th Annual Design Automation ConferenceDAC, 2013.

Contents (185 items)

Proceedings of the 50th Annual Design Automation Conference
DAC, 2013.