Travelled to:2 × France
2 × Germany
5 × USA
Collaborated with:K.Chakraborty D.M.Ancajas K.Bhardwaj H.Chen P.Banerjee D.Manzi J.M.Nickerson B.Cozzens
Talks about:no (6) algorithm (3) rout (3) age (3) microprocessor (2) heterogen (2) multicor (2) pipelin (2) perform (2) violat (2)
Person: Sanghamitra Roy
DBLP: Roy:Sanghamitra
Contributed to:
20152014
2014201320132012201220112004Wrote 12 papers:
- DAC-2015-ChenMRC #execution #paradigm #performance
- Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks (HC, DM, SR, KC), p. 6.
- DAC-2014-AncajasCR #named
- Fort-NoCs: Mitigating the Threat of a Compromised NoC (DMA, KC, SR), p. 6.
- DATE-2014-ChenRC #adaptation #design #named #pipes and filters
- DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors (HC, SR, KC), pp. 1–6.
- DAC-2013-AncajasCR #3d #manycore #memory management #named
- DMR3D: dynamic memory relocation in 3D multicore systems (DMA, KC, SR), p. 9.
- DAC-2013-AncajasNCR #architecture
- HCI-tolerant NoC router microarchitecture (DMA, JMN, KC, SR), p. 10.
- DAC-2013-ChakrabortyCRA #pipes and filters
- Efficiently tolerating timing violations in pipelined microprocessors (KC, BC, SR, DMA), p. 8.
- DATE-2013-AncajasCR #approach
- Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach (DMA, KC, SR), pp. 1032–1037.
- DAC-2012-BhardwajCR #adaptation #algorithm #towards
- Towards graceful aging degradation in NoCs through an adaptive routing algorithm (KB, KC, SR), pp. 382–391.
- DAC-2012-RoyC #analysis #predict
- Predicting timing violations through instruction-level path sensitization analysis (SR, KC), pp. 1074–1081.
- DATE-2012-BhardwajCR #algorithm
- An MILP-based aging-aware routing algorithm for NoCs (KB, KC, SR), pp. 326–331.
- DATE-2011-ChakrabortyR #manycore
- Topologically homogeneous power-performance heterogeneous multicore systems (KC, SR), pp. 125–130.
- DAC-2004-RoyB #algorithm #design #fixpoint #float #matlab
- An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design (SR, PB), pp. 484–487.