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design (41)
verif (39)
power (30)
high (20)
base (19)

Stem microprocessor$ (all stems)

169 papers:

DATEDATE-2015-ConstantinWKCB
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment (JC, LW, GK, AC, AB), pp. 381–386.
DATEDATE-2015-KainthKNVT #obfuscation
Hardware-assisted code obfuscation for FPGA soft microprocessors (MK, LK, CN, SGV, RT), pp. 127–132.
DATEDATE-2015-OborilET #monitoring #online
High-resolution online power monitoring for modern microprocessors (FO, JE, MBT), pp. 265–268.
HPCAHPCA-2015-HayesPUCV #algorithm #architecture #novel #sorting
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors (TH, OP, OSÜ, AC, MV), pp. 26–38.
DATEDATE-2014-ChenRC #adaptation #design #named #pipes and filters
DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors (HC, SR, KC), pp. 1–6.
DATEDATE-2014-DweikAD #array #exception #fault
Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures (WD, MA, MD), pp. 1–6.
DATEDATE-2014-KondoKSWTNWAMKUKN #design #embedded #evaluation #fine-grained
Design and evaluation of fine-grained power-gating for embedded microprocessors (MK, HK, RS, MW, JT, MN, WW, HA, KM, MK, KU, TK, HN), pp. 1–6.
DATEDATE-2014-WuWDHYY #in memory #integration #manycore #memory management
A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os (SSW, KW, SMPD, TYH, MY, HY), pp. 1–4.
DACDAC-2013-ChakrabortyCRA #pipes and filters
Efficiently tolerating timing violations in pipelined microprocessors (KC, BC, SR, DMA), p. 8.
DACDAC-2013-DinakarraoWY #3d #multi #reduction
Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor (SMPD, KW, HY), p. 6.
DACDAC-2013-KarnikPB #power management
Power management and delivery for high-performance microprocessors (TK, M(P, SB), p. 3.
DATEDATE-2013-ChenM #analysis #modelling #reliability
System-level modeling and microprocessor reliability analysis for backend wearout mechanisms (CCC, LM), pp. 1615–1620.
DATEDATE-2013-WangYWZ #3d #configuration management #manycore #network
3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors (KW, HY, BW, CZ), pp. 1643–1648.
TAPTAP-2013-BruckerFNW #case study #generative
Test Program Generation for a Microprocessor — A Case-Study (ADB, AF, YN, BW), pp. 76–95.
DACDAC-2012-KongC #3d #process
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors (JK, SWC), pp. 1197–1206.
DATEDATE-2012-CampagnaV #architecture #detection #fault #hybrid #validation
An hybrid architecture to detect transient faults in microprocessors: An experimental validation (SC, MV), pp. 1433–1438.
DATEDATE-2012-WangTLG #runtime
Runtime power estimator calibration for high-performance microprocessors (HW, SXDT, XL, AG), pp. 352–357.
LCTESLCTES-2012-KhudiaWM #embedded #fault #performance #using
Efficient soft error protection for commodity embedded microprocessors using profile information (DSK, GW, SAM), pp. 99–108.
DACDAC-2011-HenrySN #embedded #power management
A case for NEMS-based functional-unit power gating of low-power embedded microprocessors (MBH, MS, LN), pp. 872–877.
DACDAC-2011-NandakumarM #3d #layout
Layout effects in fine grain 3D integrated regular microprocessor blocks (VSN, MMS), pp. 639–644.
DACDAC-2010-ThomptoH #fault tolerance #verification
Verification for fault tolerance of the IBM system z microprocessor (BWT, BH), pp. 525–530.
DATEDATE-2010-EguiaTSPT #behaviour #design #manycore #modelling
General behavioral thermal modeling and characterization for multi-core microprocessor design (TJAE, SXDT, RS, EHP, MT), pp. 1136–1141.
DATEDATE-2010-LiZYZ #functional
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors (LL, YZ, JY, JZ), pp. 411–416.
DATEDATE-2010-PanHL #fault #named
IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults (SP, YH, XL), pp. 238–243.
DATEDATE-2010-ZhangLL #approach #markov #modelling #simulation #using #verification
An abstraction-guided simulation approach using Markov models for microprocessor verification (TZ, TL, XL), pp. 484–489.
DACDAC-2009-BaumannSP #architecture #assessment #design #embedded #robust
Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors (TB, DSL, CP), pp. 947–950.
HPCAHPCA-2009-Hill
Opportunities beyond single-core microprocessors (MDH), pp. 143–144.
PPoPPPPoPP-2009-Hill
Opportunities beyond single-core microprocessors (MDH), p. 97.
DACDAC-2008-TurumellaS #concurrent #thread #verification
Assertion-based verification of a 32 thread SPARCTM CMT microprocessor (BT, MS), pp. 256–261.
DATEDATE-2008-Brand #design #manycore #optimisation
Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity Considerations (HJB), pp. 938–939.
DATEDATE-2008-ZhouPB #analysis #generative #metric #modelling #using
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement (YZ, SP, SB), pp. 98–103.
HPCAHPCA-2008-JoshiEJI #automation #generative
Automated microprocessor stressmark generation (AMJ, LE, LKJ, CI), pp. 229–239.
DACDAC-2007-HwuRUKGSKBMTNLFP #modelling #parallel #programming
Implicitly Parallel Programming Models for Thousand-Core Microprocessors (WmWH, SR, SZU, JHK, IG, SSS, REK, SSB, AM, SCT, NN, SSL, MIF, SJP), pp. 754–759.
DACDAC-2007-KaoHL #embedded #integration #multi
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration (CFK, IJH, CHL), pp. 477–482.
DACDAC-2007-PuttaswamyL #3d #scalability
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors (KP, GHL), pp. 622–625.
DACDAC-2007-YangHH #automation #behaviour #design #verification
Automatic Verification of External Interrupt Behaviors for Microprocessor Design (FCY, WKH, IJH), pp. 896–901.
DATEDATE-2007-BorkarJS #integration
Microprocessors in the era of terascale integration (SB, NPJ, PS), pp. 237–242.
DATEDATE-2007-LeGB #pervasive #verification
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor (TL, TG, JB), pp. 219–224.
DATEDATE-2007-MathaikuttySKLD #design #fault #generative #testing #validation
Design fault directed test generation for microprocessor validation (DM, SKS, SVK, DJL, AD), pp. 761–766.
DATEDATE-2007-SirowyWLV #clustering
Two-level microprocessor-accelerator partitioning (SS, YW, SL, FV), pp. 313–318.
CASECASE-2006-LuLYW #design #embedded
Design of Bio-fermentation Control System Based on the Embedded Microprocessor (XL, YL, HY, WW), pp. 540–545.
DACDAC-2006-Gluska #verification
Practical methods in coverage-oriented verification of the merom microprocessor (AG), pp. 332–337.
DACDAC-2006-KarlBSM #modelling #reliability
Reliability modeling and management in dynamic microprocessor-based systems (EK, DB, DS, TNM), pp. 1057–1060.
DACDAC-2006-MukherjeeM
Systematic temperature sensor allocation and placement for microprocessors (RM, SOM), pp. 542–547.
DACDAC-2006-StojanovicBDW #effectiveness #implementation #queue
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors (VS, RIB, JD, RW), pp. 705–708.
DACDAC-2006-WuJYLT #estimation #functional
A systematic method for functional unit power estimation in microprocessors (WW, LJ, JY, PL, SXDT), pp. 554–557.
DATEDATE-2006-ViswanathAJ #automation #pipes and filters #power management
Automatic insertion of low power annotations in RTL for pipelined microprocessors (VV, JAA, WAHJ), pp. 496–501.
ASPLOSASPLOS-2006-ShyamCPBA #fault #low cost #pipes and filters
Ultra low-cost defect protection for microprocessor pipelines (SS, KC, SP, VB, TMA), pp. 73–82.
HPCAHPCA-2006-KumarA #concurrent #detection #fault #performance
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors (SK, AA), pp. 212–221.
DACDAC-2005-AdirABPS #approach #architecture #testing #verification
A generic micro-architectural test plan approach for microprocessor verification (AA, HA, EB, OP, KS), pp. 769–774.
DATEDATE-2005-StittV #approach #clustering #decompiler
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms (GS, FV), pp. 396–397.
CAVCAV-2005-Bentley #validation
Validating a Modern Microprocessor (BB), pp. 2–4.
DACDAC-2004-ClabesFSDCPDMPFSLGWSRGRKMD #design #implementation
Design and implementation of the POWER5 microprocessor (JGC, JF, MS, JD, SGC, DWP, JD, PM, LP, MSF, BS, ML, MG, JW, NSS, SLR, GG, PR, RNK, JM, JSD), pp. 670–672.
DACDAC-2004-Kung #design
Timing closure for low-FO4 microprocessor design (DSK), pp. 265–266.
DACDAC-2004-OhbaT #design #embedded #using
An SoC design methodology using FPGAs and embedded microprocessors (NO, KT), pp. 747–752.
DACDAC-2004-TakayanagiSPSL
A dual-core 64b ultraSPARC microprocessor for dense server applications (TT, JLS, BP, JS, ASL), pp. 673–677.
DACDAC-2004-VassighiKNSYLCSD #design #optimisation
Design optimizations for microprocessors at low temperature (AV, AK, SN, GS, YY, SL, GC, MS, VD), pp. 2–5.
DATEDATE-v1-2004-Velev #performance #verification
Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors (MNV), pp. 266–271.
SACSAC-2004-PanagopoulosPP #attribute grammar #evaluation #hardware
A hardware extension of the RISC microprocessor for Attribute Grammar evaluation (IP, CP, GKP), pp. 897–904.
ASPLOSASPLOS-2004-WuJMC #multi #online
Formal online methods for voltage/frequency control in multiple clock domain microprocessors (QW, PJ, MM, DWC), pp. 248–259.
HPCAHPCA-2004-JosephHM #analysis #case study #design #experience
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization (RJ, ZH, MM), pp. 36–47.
HPCAHPCA-2004-MakineniI #architecture
Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor (SM, RRI), pp. 152–163.
CAVCAV-2004-Hunt #verification
Mechanical Mathematical Methods for Microprocessor Verification (WAHJ), pp. 523–533.
DACDAC-2003-AmdeBS #automation #design
Automating the design of an asynchronous DLX microprocessor (MA, IB, CPS), pp. 502–507.
DACDAC-2003-AndoYISAMMMOYSKYS #generative
A 1.3GHz fifth generation SPARC64 microprocessor (HA, YY, AI, IS, TA, KM, TM, TM, SO, HY, YS, AK, RY, HS), pp. 702–705.
DACDAC-2003-ChanKLNR #performance #physics #synthesis
Physical synthesis methodology for high performance microprocessors (YHC, PK, LBL, GAN, TER), pp. 696–701.
DACDAC-2003-Schubert #verification
High level formal verification of next-generation microprocessors (TS), pp. 1–6.
DATEDATE-2003-CornoCRS #automation #generative
Fully Automatic Test Program Generation for Microprocessor Cores (FC, GC, MSR, GS), pp. 11006–11011.
DATEDATE-2003-QinM #flexibility #formal method #modelling #simulation
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation (WQ, SM), pp. 10556–10561.
DATEDATE-2003-RebaudengoRV #analysis #fault #pipes and filters
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor (MR, MSR, MV), pp. 10602–10607.
HPCAHPCA-2003-LiBCVR #reduction
Deterministic Clock Gating for Microprocessor Power Reduction (HL, SB, YC, TNV, KR), pp. 113–122.
HPCAHPCA-2003-SakamotoKIAUMK #analysis #architecture #enterprise #performance
Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems (MS, AK, AI, TA, HU, KM, YK), pp. 141–152.
CAVCAV-2003-LahiriB #deduction #verification
Deductive Verification of Advanced Out-of-Order Microprocessors (SKL, REB), pp. 341–353.
DACDAC-2002-GuptaSDGNKKR #coordination #performance #synthesis
Coordinated transformations for high-level synthesis of high performance microprocessor blocks (SG, NS, NDD, RKG, AN, TK, MK, SR), pp. 898–903.
DACDAC-2002-KarnikYTWBGDB #optimisation #performance
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors (TK, YY, JT, LW, SMB, VG, VD, SB), pp. 486–491.
DATEDATE-2002-MishraDNT #automation #execution #functional #multi #pipes and filters #verification
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units (PM, NDD, AN, HT), pp. 36–43.
DATEDATE-2002-PenzesM #energy #estimation
An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor (PIP, AJM), pp. 640–647.
DATEDATE-2002-PonomarevKG #estimation #named
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors (DP, GK, KG), pp. 124–129.
DATEDATE-2002-Velev #similarity #using #verification
Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer (MNV), pp. 28–35.
DACDAC-2001-Bentley #validation
Validating the Intel Pentium 4 Microprocessor (BB), pp. 244–248.
DACDAC-2001-LeeT #fault #verification
Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling System (RL, BT), pp. 822–827.
DACDAC-2001-MneimnehAWCSA #hybrid #scalability #verification
Scalable Hybrid Verification of Complex Microprocessors (MNM, FAA, CTW, SC, KAS, TMA), pp. 41–46.
DACDAC-2001-NorthropL #design
A Semi-Custom Design Flow in High-Performance Microprocessor Design (GAN, PFL), pp. 426–431.
DACDAC-2001-VelevB #effectiveness #satisfiability #verification
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors (MNV, REB), pp. 226–231.
DATEDATE-2001-CornoRSV #on the
On the test of microprocessor IP cores (FC, MSR, GS, MV), pp. 209–213.
DATEDATE-2001-HsiehCP #analysis #simulation
Microprocessor power analysis by labeled simulation (CTH, LC, MP), pp. 182–189.
DATEDATE-2001-Narita #game studies #multi
SH-4 RISC microprocessor for multimedia, game machine (SN), pp. 699–701.
DATEDATE-2001-ZengABA #identification
Full chip false timing path identification: applications to the PowerPCTM microprocessors (JZ, MSA, JB, JAA), pp. 514–519.
TACASTACAS-2001-Velev #abstraction #automation #verification
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors (MNV), pp. 252–267.
HPCAHPCA-2001-BrooksM
Dynamic Thermal Management for High-Performance Microprocessors (DMB, MM), pp. 171–182.
CAVCAV-2001-BjesseLM #debugging #satisfiability #using
Finding Bugs in an α Microprocessor Using Satisfiability Solvers (PB, TL, AM), pp. 454–464.
DACDAC-2000-AagaardJKKS #algorithm #verification
Formal verification of iterative algorithms in microprocessors (MA, RBJ, RK, KRK, CJHS), pp. 201–206.
DACDAC-2000-BrandoleseFSS #energy #estimation
An instruction-level functionally-based energy estimation model for 32-bits microprocessors (CB, WF, FS, DS), pp. 346–351.
DACDAC-2000-LiuNPS
Impact of interconnect variations on the clock skew of a gigahertz microprocessor (YL, SRN, LTP, AJS), pp. 168–171.
DACDAC-2000-NiemierKK #design #novel #quantum #tool support
A design of and design tools for a novel quantum dot based microprocessor (MTN, MJK, PMK), pp. 227–232.
DACDAC-2000-PoslusznyABCDFHKKLMNPPSTV #design
“Timing closure by design”, a high frequency microprocessor design methodology (SDP, NA, DB, PKC, SHD, BKF, HPH, NK, OK, KL, DM, KJN, JP, JP, JS, OT, PV), pp. 712–717.
DACDAC-2000-QuKUP #estimation
Function-level power estimation methodology for microprocessors (GQ, NK, KU, MP), pp. 810–813.
DACDAC-2000-VelevB #branch #exception #functional #multi #predict #verification
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction (MNV, REB), pp. 112–117.
DACDAC-2000-YenY #design #multi #verification
Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor (JTY, QRY), pp. 718–723.
CAVCAV-2000-Velev #execution #verification
Formal Verification of VLIW Microprocessors with Speculative Execution (MNV), pp. 296–311.
DACDAC-1999-CampenhoutMH #design #generative #pipes and filters #testing #verification
High-Level Test Generation for Design Verification of Pipelined Microprocessors (DVC, TNM, JPH), pp. 185–188.
DACDAC-1999-ChangLPK #using #verification
Verification of a Microprocessor Using Real World Applications (YSC, SL, ICP, CMK), pp. 181–184.
DACDAC-1999-PapachristouMN #testing
Microprocessor Based Testing for Core-Based System on Chip (CAP, FM, MN), pp. 586–591.
DACDAC-1999-RaimiA #detection
Detecting False Timing Paths: Experiments on PowerPC Microprocessors (RR, JAA), pp. 737–741.
DACDAC-1999-ShenABHKGCH #functional #verification
Functional Verification of the Equator MAP1000 Microprocessor (JS, JAA, DB, TH, MK, GG, CcC, GH), pp. 169–174.
DACDAC-1999-VelevB #pipes and filters #similarity #verification
Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors (MNV, REB), pp. 397–401.
DATEDATE-1999-FournierAL #functional #product line #using #verification
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family (LF, YA, ML), pp. 434–441.
FMFM-v1-1999-LotzKW #hardware #security
A Formal Security Model for Microprocessor Hardware (VL, VK, GW), pp. 718–737.
CAVCAV-1999-BiereCRZ #model checking #safety #using
Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs (AB, EMC, RR, YZ), pp. 60–71.
DACDAC-1998-DharchoudhuryPBVTB #analysis #design #network
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors (AD, RP, DB, RV, BT, DB), pp. 738–743.
DACDAC-1998-GowanBJ #design
Power Considerations in the Design of the Alpha 21264 Microprocessor (MKG, LLB, DBJ), pp. 726–731.
DACDAC-1998-HattoriNSNUTS #design
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4 (TH, YN, MS, SN, KU, TT, RS), pp. 246–249.
DACDAC-1998-NassifDH #modelling #robust #verification
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.
DACDAC-1998-TaylorQBDHHR #functional #multi #verification
Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor — The DEC Alpha 21264 Microprocessor (SAT, MQ, DB, ND, SH, JH, CR), pp. 638–643.
DACDAC-1998-TiwariSRMPB
Reducing Power in High-Performance Microprocessors (VT, DS, SR, GM, RP, FB), pp. 732–737.
DACDAC-1998-WangAK #array #automation #evaluation #generative #using #verification
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation (LCW, MSA, NK), pp. 534–537.
DATEDATE-1998-WangAZ #array #design #effectiveness #validation
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays (LCW, MSA, JZ), pp. 273–277.
CAVCAV-1998-HosabettuSG #correctness #pipes and filters #proving
Decomposing the Proof of Correctness of pipelined Microprocessors (RH, MKS, GG), pp. 122–134.
DACDAC-1997-GrundmannDAR #design #performance #using
Designing High Performance CMOS Microprocessors Using Full Custom Techniques (WJG, DD, RLA, NLR), pp. 722–727.
DACDAC-1997-YimHPCYOPK #design #verification
A C-Based RTL Design Verification Methodology for Complex Microprocessor (JSY, YHH, CJP, HC, WSY, HSO, ICP, CMK), pp. 83–88.
DATEEDTC-1997-NarayananSKLB #fault
A fault diagnosis methodology for the UltraSPARCTM-I microprocessor (SN, RS, RPK, MEL, SBN), pp. 494–500.
CAVCAV-1997-BarrettM #design #model checking
Model Checking in a Microprocessor Design Project (GB, AM), pp. 214–225.
CAVCAV-1997-SawadaH #approach #pipes and filters #verification
Trace Table Based Approach for Pipeline Microprocessor Verification (JS, WAHJ), pp. 364–375.
DACDAC-1996-Burch #verification
Techniques for Verifying Superscalar Microprocessors (JRB), pp. 552–557.
DACDAC-1996-HosseiniMK #analysis #code generation #functional #verification
Code Generation and Analysis for the Functional Verification of Microprocessors (AH, DM, PK), pp. 305–310.
DACDAC-1996-KantrowitzN #analysis #correctness #simulation #verification #what
I’m Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor (MK, LMN), pp. 325–330.
DACDAC-1996-LevittO #pipes and filters #scalability #verification
A Scalable Formal Verification Methodology for Pipelined Microprocessors (JRL, KO), pp. 558–563.
DACDAC-1996-MonacoHR #functional #verification
Functional Verification Methodology for the PowerPC 604 Microprocessor (JM, DH, RR), pp. 319–324.
HPCAHPCA-1996-CvetanovicB #performance #specification #using
Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads (ZC, DB), pp. 270–280.
HPCAHPCA-1996-GulatiB #parallel #performance #thread
Performance Study of a Multithreaded Superscalar Microprocessor (MG, NB), pp. 291–301.
DACDAC-1995-CaoABDDDDDDFGGGILMMMPPPRRSSSSVWYYZZ #design
CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc (AC, AA, JB, PD, PD, PD, MD, TD, MD, PF, OG, DG, SG, JI, LL, JM, MM, SM, PP, AP, RP, SR, NR, PS, SS, RS, BS, WV, MW, PY, RKY, JZ, GBZ), pp. 19–22.
DACDAC-1995-LiaoDKTW #embedded #optimisation
Code Optimization Techniques for Embedded DSP Microprocessors (SYL, SD, KK, SWKT, ARW), pp. 599–604.
DACDAC-1995-MalleyD #logic #verification
Logic Verification Methodology for PowerPC Microprocessors (CHM, MD), pp. 234–240.
ICDARICDAR-v2-1995-ChinW #recognition
A microprocessor-based optical character recognition check reader (FYLC, FW), pp. 982–985.
DACDAC-1994-BeattyB #simulation #using #verification
Formally Verifying a Microprocessor Using a Simulation Methodology (DLB, REB), pp. 596–602.
DACDAC-1994-BhagwatiD #automation #pipes and filters #verification
Automatic Verification of Pipelined Microprocessors (VB, SD), pp. 603–608.
DACDAC-1994-Fox #design
The Design of High-Performance Microprocessors at Digital (TFF), pp. 586–591.
DACDAC-1994-GuptaS #automation #design #multi #verification
Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs (APG, DPS), pp. 113–119.
DACDAC-1994-HuangD #pipes and filters #set #synthesis
Synthesis of Instruction Sets for Pipelined Microprocessors (IJH, AMD), pp. 5–11.
DATEEDAC-1994-GreinerLWW #complexity #design #library
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library (AG, LL, FW, LW), pp. 9–13.
SACSAC-1994-GrubbsHTM #simulation
Motorola 68040 microprocessor simulation for the Sun Workstation (TG, BH, RT, SM), pp. 25–30.
ASPLOSASPLOS-1994-ArgadeCT #monitoring #operating system #runtime
A Technique for Monitoring Run-Time Dynamics of an Operating System and a Microprocessor Executing User Applications (PVA, DKC, CT), pp. 122–131.
ASPLOSASPLOS-1994-UptonHMB #resource management
Resource Allocation in a High Clock Rate Microprocessor (MU, TH, TNM, RBB), pp. 98–109.
CAVCAV-1994-BurchD #automation #pipes and filters #verification
Automatic verification of Pipelined Microprocessor Control (JRB, DLD), pp. 68–80.
DACDAC-1993-GanapathyA #pseudo
Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor (GG, JAA), pp. 550–555.
DACDAC-1992-PyoSHPKTCCLWD #automation #design
Application-Driven Design Automation for Microprocessor Design (IP, CLS, IJH, KRP, YSK, CYT, HTC, GC, SL, SW, AMD), pp. 512–517.
CADECADE-1992-BoyerY #automation #correctness #proving #source code
Automated Correctness Proofs of Machine Code Programs for a Commercial Microprocessor (RSB, YY), pp. 416–430.
CAVCAV-1992-HamaguchiHY #branch #design #logic #using #verification
Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic (KH, HH, SY), pp. 206–219.
DACDAC-1989-LukD #layout #multi #optimisation
Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout (WKL, AAD), pp. 110–115.
ASPLOSASPLOS-1989-CohnGLT #architecture #compilation #trade-off #word
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor (RC, TRG, MSL, PST), pp. 2–14.
DACDAC-1988-LinH #automation #functional #generative
Automatic Functional Test Program Generation for Microprocessors (CSL, HFH), pp. 605–608.
ASPLOSASPLOS-1987-DitzelM #c #design #programming language #trade-off
Design Tradeoffs to Support the C Programming Language in the CRISP Microprocessor (DRD, HRM), pp. 158–163.
DACDAC-1985-OdawaraTO #data flow #diagrams
Diagrammatic function description of microprocessor and data-flow processor (GO, MT, IO), pp. 731–734.
DACDAC-1984-KarpovskyM #approach #testing
An approach to the testing of microprocessors (MGK, RVM), pp. 196–202.
DACDAC-1984-RajPG #synthesis
Microprocessor synthesis (VKR, BMP, DDG), pp. 676–678.
DACDAC-1983-Pawlak #modelling
Microprocessor systems modeling with MODLAN (AP), p. 24.
DACDAC-1983-Pawlak83a #modelling
Microprocessor systems modeling with MODLAN (AP), pp. 804–811.
DACDAC-1982-BellonLSSVGI #automation #generative #source code
Automatic generation of microprocessor test programs (CB, AL, SS, GS, RV, FG, MI), pp. 566–573.
VLDBVLDB-1982-Hawthorn #assembly #database #statistics #tuple
Microprocessor Assisted Tuple Access, Decompression and Assembly for Statistical Database Systems (PBH), pp. 223–233.
ASPLOSASPLOS-1982-AhujaA #architecture #communication #hardware #multi #scheduling
A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling (SA, AA), pp. 205–209.
ASPLOSASPLOS-1982-BerenbaumCL #operating system
The Operating System and Language Support Features of the BELLMAC-32 Microprocessor (ADB, MWC, PML), pp. 30–38.
DACDAC-1979-Lattin #design #problem
VLSI design methodology the problem of the 80’s for microprocessor design (BL), pp. 548–549.
ICSEICSE-1979-AnconaDD #development #using
Cross Software Development for Microprocessors Using a Translator Writing System (MA, GD, ELD), pp. 399–402.
ICSEICSE-1979-DAgapayeff #framework #on the
On Microprocessors: A Platform for True Program Portability with Examples from Microcobal (AD), pp. 332–339.
DACDAC-1978-RossL #design
Computer aided design of microprocessor-based systems (AAR, HHLJ), pp. 227–230.
VLDBVLDB-1978-OzkarahanO #composition #database
Microprocessor Based Modular Database Processors (EAO, KO), pp. 300–311.
DACDAC-1977-ArmstrongW #simulation
Simulation techniques for microprocessors (JRA, GW), pp. 225–229.
DACDAC-1976-Matelan #automation #design #realtime
Automating the design of microprocessor-based real time control systems (MNM), pp. 462–469.
SOSPSOSP-1975-ArdenB #architecture #multi
A Multi-Microprocessor Computer System Architecture (BWA, ADB), pp. 114–121.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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