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Travelled to:
1 × USA
Collaborated with:
M.Marek-Sadowska
Talks about:
placement (1) sequenti (1) circuit (1) budget (1) applic (1) delay (1) fpga (1)

Person: Chao-Yang Yeh

DBLP DBLP: Yeh:Chao=Yang

Contributed to:

DAC 20032003

Wrote 1 papers:

DAC-2003-YehM
Delay budgeting in sequential circuit with application on FPGA placement (CYY, MMS), pp. 202–207.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.