BibSLEIGH — Malgorzata

Travelled to:

18 × USA
2 × Germany
5 × France

Collaborated with:

K.Wang K.Cheng A.Vittal Y.Ran S.Chang B.Hu L.H.Chen V.S.Nandakumar C.Tsai Y.Wu C.J.Chang A.Mukherjee L.Macchiarulo M.T.Lee A.Kondratyev Y.Watanabe D.I.Cheng X.Qiu H.Jiang Q.Liu C.Yeh T.Xiao R.Dutta ∅ D.Chang C.Lin W.Maly Y.Lin F.Brewer A.Singh S.Shu S.Lin E.S.Kuh Y.Su D.Wang C.Cheng P.Suaris R.Sudhakar S.I.Long Y.Jiang A.Krstic K.Tsai S.Hellebrand J.Rajski D.C.Wang N.S.Woo T.Aikyo K.Chen D.Chai K.H.Tseng

Talks about:

power (12) design (8) optim (8) layout (7) use (7) function (6) minim (6) logic (6) nois (6) crosstalk (5)

Person: Malgorzata Marek-Sadowska

DBLP: Marek-Sadowska:Malgorzata

Contributed to:

2014

2012

2011

2008

2007

2004

2003

2002

2001

2000

1999

1998

1997

1996

1995

1994

1990

1989

1985

Wrote 48 papers:

DAC-2014-NandakumarM #analysis: System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs (VSN, MMS), p. 6.
DAC-2012-QiuM #question #scalability: Can pin access limit the footprint scaling? (XQ, MMS), pp. 1100–1106.
DAC-2011-NandakumarM #3d #layout: Layout effects in fine grain 3D integrated regular microprocessor blocks (VSN, MMS), pp. 639–644.
DAC-2008-JiangM #power management #reduction #scheduling: Power gating scheduling for power/ground noise reduction (HJ, MMS), pp. 980–985.
DAC-2007-MalyLM #design: OPC-Free and Minimally Irregular IC Design Style (WM, YWL, MMS), pp. 954–957.
DAC-2007-SuWCM #design #optimisation #performance: An Efficient Mechanism for Performance Optimization of Variable-Latency Designs (YSS, DCW, SCC, MMS), pp. 976–981.
DAC-2004-LiuM #estimation: Pre-layout wire length and congestion estimation (QL, MMS), pp. 582–587.
DAC-2004-RanM #configuration management #design #on the: On designing via-configurable cell blocks for regular fabrics (YR, MMS), pp. 198–203.
DAC-2004-WangM #constraints #power management: Buffer sizing for clock power minimization subject to general skew constraints (KW, MMS), pp. 159–164.
DATE-v2-2004-RanKWM #analysis: Eliminating False Positives in Crosstalk Noise Analysis (YR, AK, YW, MMS), pp. 1192–1197.
DAC-2003-ChaiKRTWM #analysis: Temporofunctional crosstalk noise analysis (DC, AK, YR, KHT, YW, MMS), pp. 860–863.
DAC-2003-HuM #clustering #predict: Wire length prediction based clustering and its application in placement (BH, MMS), pp. 800–805.
DAC-2003-HuWKM #library: Gain-based technology mapping for discrete-size cell libraries (BH, YW, AK, MMS), pp. 574–579.
DAC-2003-RanM: Crosstalk noise in FPGAs (YR, MMS), pp. 944–949.
DAC-2003-WangM #multi #network #optimisation #power management #using: On-chip power supply network optimization using multigrid-based technique (KW, MMS), pp. 113–118.
DAC-2003-YehM: Delay budgeting in sequential circuit with application on FPGA placement (CYY, MMS), pp. 202–207.
DATE-2003-WangM #multi #optimisation #using: Power/Ground Mesh Area Optimization Using Multigrid-Based Technique (KW, MMS), pp. 10850–10855.
DAC-2002-ChenMB02a: Coping with buffer delay change due to power and ground noise (LHC, MMS, FB), pp. 860–865.
DATE-2002-ChenM #design #metric #physics: Closed-Form Crosstalk Noise Metrics for Physical Design Applications (LHC, MMS), pp. 812–819.
DATE-2002-MukherjeeWCM #component: Sizing Power/Ground Meshes for Clocking and Computing Circuit Components (AM, KW, LHC, MMS), pp. 176–183.
DAC-2001-ChangWM #logic #using: Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques (CWJC, KW, MMS), pp. 97–102.
DAC-2001-SinghMM #latency: Latency and Latch Count Minimization in Wave Steered Circuits (AS, AM, MMS), pp. 383–388.
DAC-2001-XiaoM #analysis #correlation #functional #identification: Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification (TX, MMS), pp. 653–656.
DATE-2001-ChangHM #functional #optimisation #symmetry #using: In-place delay constrained power optimization using functional symmetries (CWJC, BH, MMS), pp. 377–382.
DAC-2000-ChangCSM #detection #functional #performance #symmetry #using: Fast post-placement rewiring using easily detectable functional symmetries (CWJC, CKC, PS, MMS), pp. 286–289.
DAC-2000-MacchiaruloM: Wave-steering one-hot encoded FSMs (LM, MMS), pp. 357–360.
DATE-2000-MacchiaruloSM: Wave Steered FSMs (LM, SMS, MMS), pp. 270–276.
DAC-1999-MukherjeeSML #layout #novel #synthesis: Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique (AM, RS, MMS, SIL), pp. 466–471.
DATE-1998-ChangCML #functional #testing: Functional Scan Chain Testing (DC, KTC, MMS, MTCL), pp. 278–283.
DAC-1997-ChangLMAC #approach #synthesis: A Test Synthesis Approach to Reducing BALLAST DFT Overhead (DC, MTCL, MMS, TA, KTC), pp. 466–471.
DAC-1997-JiangKCM #logic #optimisation #performance: Post-Layout Logic Restructuring for Performance Optimization (YMJ, AK, KTC, MMS), pp. 662–665.
DAC-1997-TsaiHRM #generative #named #random: STARBIST: Scan Autocorrelated Random Pattern Generation (KHT, SH, JR, MMS), pp. 472–477.
DAC-1996-ChengCWM #estimation #hybrid: A New Hybrid Methodology for Power Estimation (DIC, KTC, DCW, MMS), pp. 439–444.
DAC-1996-LinMCL #logic: Test Point Insertion: Scan Paths through Combinational Logic (CCL, MMS, KTC, MTCL), pp. 268–273.
DAC-1996-TsaiM #logic #multi #synthesis: Multilevel Logic Synthesis for Arithmetic Functions (CCT, MMS), pp. 242–247.
DAC-1995-ChangMC #algorithm #performance #set: An Efficient Algorithm for Local Don’t Care Sets Calculation (SCC, MMS, KTC), pp. 663–667.
DAC-1995-LinCCMC #logic #synthesis: Logic Synthesis for Engineering Change (CCL, KCC, SCC, MMS, KTC), pp. 647–652.
DAC-1995-VittalM #design: Power Optimal Buffered Clock Tree Design (AV, MMS), pp. 497–502.
DAC-1995-VittalM95a #design: Power Distribution Topology Design (AV, MMS), pp. 503–507.
DAC-1995-WuM #2d #approach #optimisation #orthogonal: Orthogonal Greedy Coupling — A New Optimization Approach to 2-D FPGA Routing (YLW, MMS), pp. 568–573.
DAC-1994-ChangCWM #layout #logic #synthesis: Layout Driven Logic Synthesis for FPGAs (SCC, KTC, NSW, MMS), pp. 308–313.
DAC-1994-TsaiM #using: Boolean Matching Using Generalized Reed-Muller Forms (CCT, MMS), pp. 339–344.
DAC-1994-VittalM #design #using: Minimal Delay Interconnect Design Using Alphabetic Trees (AV, MMS), pp. 392–396.
EDAC-1994-ChangCM #multi: Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions (SCC, DIC, MMS), pp. 620–624.
EDAC-1994-WuM #2d #array #performance #programmable: An Efficient Router for 2-D Field Programmable Gate Arrays (YLW, MMS), pp. 412–416.
DAC-1990-LinMK #design #optimisation #standard: Delay and Area Optimization in Standard-Cell Design (SL, MMS, ESK), pp. 349–352.
DAC-1989-DuttaM #automation #network: Automatic Sizing of Power/Ground (P/G) Networks in VLSI (RD, MMS), pp. 783–786.
DAC-1985-Marek-Sadowska #2d #layout: Two-dimensional router for double layer layout (MMS), pp. 117–123.