BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Used together with:
base (77)
architectur (24)
system (24)
implement (23)
design (22)

Stem fpga$ (all stems)

214 papers:

CASECASE-2015-QuangTH #adaptation #using
FPGA-based sensorless PMSM speed control using adaptive extended Kalman filter (NKQ, DDT, QPH), pp. 1650–1655.
DACDAC-2015-ZhangHXHC #compilation #framework #named
CMOST: a system-level FPGA compilation framework (PZ, MH, BX, HH, JC), p. 6.
DACDAC-2015-ZhaoTDZ #pipes and filters #synthesis
Area-efficient pipelining for FPGA-targeted high-level synthesis (RZ, MT, SD, ZZ), p. 6.
DATEDATE-2015-BruggerVWTK #cpu #hybrid
Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems (CB, JAV, NW, ST, RK), pp. 1599–1602.
DATEDATE-2015-ChenZWWWZ #multi #named #pseudo #simulation
MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation (XC, GZ, HW, RW, PW, LZ), pp. 211–216.
DATEDATE-2015-GaillardonTSTOS #power management
A ultra-low-power FPGA based on monolithically integrated RRAMs (PEG, XT, JS, MT, SRO, DS, YL, GDM), pp. 1203–1208.
DATEDATE-2015-GheolbanoiuPC #adaptation #hybrid
Hybrid adaptive clock management for FPGA processor acceleration (AG, LP, SC), pp. 1359–1364.
DATEDATE-2015-GiefersPH #kernel
Accelerating arithmetic kernels with coherent attached FPGA coprocessors (HG, RP, CH), pp. 1072–1077.
DATEDATE-2015-HadjisCSHTA #multi #synthesis
Profiling-driven multi-cycling in FPGA high-level synthesis (SH, AC, RS, YHA, HT, JA), pp. 31–36.
DATEDATE-2015-HuriauxCS #design #runtime
Design flow and run-time management for compressed FPGA configurations (CH, AC, OS), pp. 1551–1554.
DATEDATE-2015-KainthKNVT #obfuscation
Hardware-assisted code obfuscation for FPGA soft microprocessors (MK, LK, CN, SGV, RT), pp. 127–132.
DATEDATE-2015-NowosielskiGBVB #design #fault tolerance #named
FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design (RN, LG, SB, GPV, HB), pp. 297–300.
DATEDATE-2015-PaganoVRCSS #configuration management
Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems (DP, MV, MR, RC, DS, MDS), pp. 920–923.
DATEDATE-2015-RamachandranHHM #fault
FPGA accelerated DNA error correction (AR, YH, WmWH, JM, DC), pp. 1371–1376.
DATEDATE-2015-SamieBHH #multi #online
Online binding of applications to multiple clock domains in shared FPGA-based systems (FS, LB, CMH, JH), pp. 25–30.
DATEDATE-2015-WangLZ #big data #named
SODA: software defined FPGA based accelerators for big data (CW, XL, XZ), pp. 884–887.
DATEDATE-2015-WeiDC #architecture #memory management #multi #scalability
A scalable and high-density FPGA architecture with multi-level phase change memory (CW, AD, DC), pp. 1365–1370.
DACDAC-2014-MoctarB #parallel
Parallel FPGA Routing based on the Operator Formulation (YOMM, PB), p. 6.
DACDAC-2014-TrimbergerM #security
FPGA Security: From Features to Capabilities to Trusted Systems (ST, JM), p. 4.
DATEDATE-2014-CilardoFGM #communication #manycore #scheduling #synthesis
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems (AC, EF, LG, AM), pp. 1–4.
DATEDATE-2014-MoralesHBHV #energy #implementation #using
Energy-efficient FPGA implementation for binomial option pricing using OpenCL (VMM, PHH, AB, EH, SV), pp. 1–6.
DATEDATE-2014-RobinoO
From Simulink to NoC-based MPSoC on FPGA (FR, ), pp. 1–4.
DATEDATE-2014-TurkyilmazCRBC #3d #integration #using
3D FPGA using high-density interconnect Monolithic Integration (OT, GC, OR, PB, FC), pp. 1–4.
DACDAC-2013-NacciRBSBA #algorithm #implementation #synthesis
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices (AAN, VR, FB, DS, IB, DA), p. 6.
DACDAC-2013-NajjarV #compilation #perspective
FPGA code accelerators — the compiler perspective (WAN, JRV), p. 6.
DATEDATE-2013-AliasDP #kernel #optimisation #synthesis
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA (CA, AD, AP), pp. 575–580.
DATEDATE-2013-CanisAB #multi #reduction #synthesis
Multi-pumping for resource reduction in FPGA high-level synthesis (AC, JHA, SDB), pp. 194–197.
DATEDATE-2013-Gomez-PradoCT #latency #optimisation #using
FPGA latency optimization using system-level transformations and DFG restructuring (DGP, MJC, RT), pp. 1553–1558.
DATEDATE-2013-SchryverTW #monte carlo #multi
A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model (CdS, PT, NW), pp. 248–253.
DATEDATE-2013-ShreejithVFL #approach #configuration management #network #using
An approach for redundancy in FlexRay networks using FPGA partial reconfiguration (SS, KV, SAF, ML), pp. 721–724.
CIKMCIKM-2013-VanderbauwhedeFACM #throughput #using
High throughput filtering using FPGA-acceleration (WV, AF, LA, SRC, MM), pp. 1245–1248.
SACSAC-2013-AzarianCWB #approach #manycore #pipes and filters
An FPGA-based multi-core approach for pipelining computing stages (AA, JMPC, SW, JB), pp. 1533–1540.
CASECASE-2012-KhanhTHH #fuzzy
FPGA-based fuzzy sliding mode control for sensorless PMSM drive (QNK, TDN, QNH, QPH), pp. 172–177.
DACDAC-2012-ZhangHY #implementation #realtime #recognition
Implementing an FPGA system for real-time intent recognition for prosthetic legs (XZ, HH, QY), pp. 169–175.
DATEDATE-2012-BattezzatiCMS #algorithm #architecture #industrial #novel
SURF algorithm in FPGA: A novel architecture for high demanding industrial applications (NB, SC, MM, LS), pp. 161–162.
DATEDATE-2012-ChatziparaskevasBP #difference #finite #parallel #using
An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes (GC, AB, IP), pp. 709–714.
DATEDATE-2012-ChenLPCPWHWM #design
Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique (CC, WSL, RP, SC, JP, JW, RTH, HSPW, SM), pp. 1361–1366.
DATEDATE-2012-MohammadiEEM #fault #injection #named
SCFIT: A FPGA-based fault injection technique for SEU fault model (AM, ME, AE, SGM), pp. 586–589.
DATEDATE-2012-ParkKSNI #classification
An FPGA-based accelerator for cortical object classification (MSP, SK, JS, VN, MJI), pp. 691–696.
DATEDATE-2012-PoulosYAVL #debugging #functional
Leveraging reconfigurability to raise productivity in FPGA functional debug (ZP, YSY, JA, AGV, BL), pp. 292–295.
DATEDATE-2012-RosiereDDW #design
An out-of-order superscalar processor on FPGA: The ReOrder Buffer design (MR, JLD, ND, FW), pp. 1549–1554.
DATEDATE-2012-TtofisT #adaptation #algorithm #hardware #implementation #realtime #towards
Towards accurate hardware stereo correspondence: A real-time FPGA implementation of a segmentation-based adaptive support weight algorithm (CT, TT), pp. 703–708.
PPoPPPPoPP-2012-AliasDP #kernel #optimisation #synthesis
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA (CA, AD, AP), pp. 285–286.
DACDAC-2011-RajavelA #clustering #named
MO-pack: many-objective clustering for FPGA CAD (STR, AA), pp. 818–823.
DATEDATE-2011-ChenGSS #analysis #performance
Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers (ZC, XG, AS, PS), pp. 1650–1655.
DATEDATE-2011-HeidmannWP #architecture #detection #throughput
Architecture and FPGA-implementation of a high throughput K+-Best detector (NH, TW, SP), pp. 240–245.
DATEDATE-2011-HuangHL #fault
Cross-layer optimized placement and routing for FPGA soft error mitigation (KH, YH, XL), pp. 58–63.
DATEDATE-2011-KesturDN #named #streaming
SHARC: A streaming model for FPGA accelerators and its application to Saliency (SK, DD, VN), pp. 1237–1242.
DATEDATE-2011-NejadMG #quality
An FPGA bridge preserving traffic quality of service for on-chip network-based systems (ABN, MEM, KG), pp. 425–430.
ICFPICFP-2011-GillF #fault #implementation #performance
Deriving an efficient FPGA implementation of a low density parity check forward error corrector (AG, AF), pp. 209–220.
SACSAC-2011-DingSW #algorithm #parallel #transitive
FPGA based parallel transitive closure algorithm (ZD, WS, MYW), pp. 393–394.
HPCAHPCA-2011-PellauerAKPE #manycore #named #simulation #using
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing (MP, MA, MAK, AP, JSE), pp. 406–417.
CASECASE-2010-LinAK #configuration management
Manipulator inverse dynamics computation on FPGA for reconfigurable applications (CSL, PKA, HK), pp. 810–815.
DACDAC-2010-CongM #reliability
LUT-based FPGA technology mapping for reliability (JC, KM), pp. 517–522.
DACDAC-2010-TanWALCPA #architecture #multi
RAMP gold: an FPGA-based architecture simulator for multiprocessors (ZT, AW, RA, YL, HC, DAP, KA), pp. 463–468.
DATEDATE-2010-HadjitheophanousTGT #3d #hardware #re-engineering #realtime #towards
Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map (SH, CT, ASG, TT), pp. 1743–1748.
DATEDATE-2010-Kheradmand-BoroujeniPL #independence #novel #process
AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics (BKB, CP, YL), pp. 339–344.
DATEDATE-2010-LazzariFMC #multi
A new quaternary FPGA based on a voltage-mode multi-valued circuit (CL, PFF, JM, LC), pp. 1797–1802.
DATEDATE-2010-LiuLKJ #adaptation #correlation #multi
FPGA-based adaptive computing for correlated multi-stream processing (ML, ZL, WK, AJ), pp. 973–976.
DATEDATE-2010-MajidK #performance
Stretching the limits of FPGA SerDes for enhanced ATE performance (AMM, DCK), pp. 202–207.
DATEDATE-2010-NassarBDDG #evaluation #named
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation (MN, SB, JLD, GD, SG), pp. 849–854.
DATEDATE-2010-StrukovM #hybrid
Monolithically stackable hybrid FPGA (DBS, AM), pp. 661–666.
DATEDATE-2010-VasicekSB #design #implementation
A method for design of impulse bursts noise filters optimized for FPGA implementations (ZV, LS, MB), pp. 1731–1736.
OOPSLAOOPSLA-2010-KouP #hardware #object-oriented #question
From OO to FPGA: fitting round objects into square hardware? (SK, JP), pp. 109–124.
DACDAC-2009-AlimohammadFC #verification
FPGA-based accelerator for the verification of leading-edge wireless systems (AA, SFF, BFC), pp. 844–847.
DACDAC-2009-CromarLC #algorithm #reduction
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation (SC, JL, DC), pp. 838–843.
DACDAC-2009-HuangV
Transmuting coprocessors: dynamic loading of FPGA coprocessors (CH, FV), pp. 848–851.
DATEDATE-2009-ArpinenKSHH #automation #integration #modelling #uml
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA (TA, TK, ES, TDH, MH), pp. 244–249.
DATEDATE-2009-BaeMV #scheduling
Exploiting clock skew scheduling for FPGA (SB, PM, NV), pp. 1524–1529.
DATEDATE-2009-ChenKLA
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing (XC, JK, SL, VA), pp. 1530–1535.
DATEDATE-2009-LomneMTRSC #evaluation #logic #robust
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA (VL, PM, LT, MR, RS, NC), pp. 634–639.
DATEDATE-2009-SanderGRBM #communication
Priority-based packet communication on a bus-shaped structure for FPGA-systems (OS, BG, CR, JB, KDMG), pp. 178–183.
DATEDATE-2009-SauvageGDMN #constraints
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints (LS, SG, JLD, YM, MN), pp. 640–645.
DATEDATE-2009-ZhuSJ #architecture #cpu #hybrid #realtime #scheduling #streaming
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures (JZ, IS, AJ), pp. 1506–1511.
SIGMODSIGMOD-2009-MuellerT #database #named #question #what
FPGA: what’s in it for a database? (RM, JT), pp. 999–1004.
LCTESLCTES-2009-McKechnieBV #debugging #monitoring #transaction
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring (PEM, MB, WV), pp. 129–136.
DACDAC-2008-BijanskyA #named
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs (SB, AA), pp. 796–799.
DACDAC-2008-ChaudhuriGFHD #configuration management #embedded #runtime
An 8x8 run-time reconfigurable FPGA embedded in a SoC (SC, SG, FF, PH, JLD), pp. 120–125.
DACDAC-2008-EguroH #pipes and filters
Enhancing timing-driven FPGA placement for pipelined netlists (KE, SH), pp. 34–37.
DACDAC-2008-HsuW #algorithm #memory management #network #power management
A generalized network flow based algorithm for power-aware FPGA memory mapping (TYH, TCW), pp. 30–33.
DACDAC-2008-HuSMH #multi #reduction
FPGA area reduction by multi-output function based sequential resynthesis (YH, VS, RM, LH), pp. 24–29.
DACDAC-2008-KuonR #architecture #automation
Automated transistor sizing for FPGA architecture exploration (IK, JR), pp. 792–795.
DATEDATE-2008-BernardiR #novel #testing
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers (PB, MSR), pp. 194–199.
DATEDATE-2008-BonesanaPS #adaptation #regular expression
An adaptable FPGA-based System for Regular Expression Matching (IB, MP, MDS), pp. 1262–1267.
DATEDATE-2008-BonnotLEGRG #approach #architecture #implementation #multi
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA (PB, FL, GE, GG, OR, PG), pp. 610–615.
DATEDATE-2008-DasMJZMC #analysis #component #detection #implementation #network #performance
An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System (AD, SM, SJ, JZ, GM, ANC), pp. 1160–1165.
DATEDATE-2008-FanBSV #algebra #design #encryption
FPGA Design for Algebraic Tori-Based Public-Key Cryptography (JF, LB, KS, IV), pp. 1292–1297.
DATEDATE-2008-LuMGB #algorithm #for free #performance
An efficient algorithm for free resources management on the FPGA (YL, TM, GG, KB), pp. 1095–1098.
DATEDATE-2008-PaulssonHB #integration #metric #power management
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs (KP, MH, JB), pp. 50–55.
DATEDATE-2008-TumeoBCCMPFS #multi #realtime
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications (AT, MB, LC, MC, MM, GP, FF, DS), pp. 1039–1044.
DATEDATE-2008-VelevG #comparison #encoding #problem #satisfiability
Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems (MNV, PG), pp. 1268–1273.
DACDAC-2007-BriskVIP #performance
Enhancing FPGA Performance for Arithmetic Circuits (PB, AKV, PI, HPA), pp. 334–337.
DACDAC-2007-ChengCW #named #power management
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches (LC, DC, MDFW), pp. 318–323.
DACDAC-2007-CzajkowskiB #using
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits (TSC, SDB), pp. 324–329.
DACDAC-2007-GolshanB
Single-Event-Upset (SEU) Awareness in FPGA Routing (SG, EB), pp. 330–333.
DATEDATE-2007-EachempatiNGVM #architecture
Assessing carbon nanotube bundle interconnect for future FPGA architectures (SE, AN, AG, NV, YM), pp. 307–312.
DATEDATE-2007-GillPW #fault #interactive #power management #symmetry
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA (BSG, CAP, FGW), pp. 1460–1465.
DATEDATE-2007-KumarHHC #configuration management #design #interactive #multi
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip (AK, AH, JH, HC), pp. 117–122.
DATEDATE-2007-LinH #interactive #reduction #statistics
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction (YL, LH), pp. 636–641.
DATEDATE-2007-NarayananHMCZ #classification #implementation #interactive
Interactive presentation: An FPGA implementation of decision tree classification (RN, DH, GM, ANC, JZ), pp. 189–194.
DATEDATE-2007-SaponaraPTCF #network #reliability
FPGA-based networking systems for high data-rate and reliable in-vehicle communications (SS, EP, MT, IDC, LF), pp. 480–485.
DATEDATE-2007-YeGM #interactive
Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio (ZY, JG, GM), pp. 21–26.
IFLIFL-2007-NaylorR #graph #reduction #using
The Reduceron: Widening the von Neumann Bottleneck for Graph Reduction Using an FPGA (MN, CR), pp. 129–146.
SACSAC-2007-LeeHPLJK #performance #regular expression #using
A high performance NIDS using FPGA-based regular expression matching (JL, SHH, NP, SWL, SJ, YSK), pp. 1187–1191.
DACDAC-2006-AtienzaVPPBMM #framework #multi #performance
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip (DA, PGDV, GP, FP, LB, GDM, JMM), pp. 618–623.
DACDAC-2006-GopalakrishnanLP #architecture #metric #using
Architecture-aware FPGA placement using metric embedding (PG, XL, LTP), pp. 460–465.
DACDAC-2006-HuLHT #reduction
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction (YH, YL, LH, TT), pp. 478–483.
DACDAC-2006-LinCC #clustering #optimisation
Optimal simultaneous mapping and clustering for FPGA delay optimization (JYL, DC, JC), pp. 472–477.
DACDAC-2006-NabaaAN #adaptation #architecture #process
An adaptive FPGA architecture with process variation compensation and reduced leakage (GN, NA, FNN), pp. 624–629.
DACDAC-2006-RadT #clustering #hybrid
A new hybrid FPGA with nanoscale clusters and CMOS routing (RMR, MT), pp. 727–730.
DACDAC-2006-SafarpourVBY #performance #satisfiability
Efficient SAT-based Boolean matching for FPGA technology mapping (SS, AGV, GB, RY), pp. 466–471.
DACDAC-2006-SrinivasanMXVS #named
FLAW: FPGA lifetime awareness (SS, PM, YX, NV, KS), pp. 630–635.
DATEDATE-2006-DensmoreDS #analysis #architecture #performance
FPGA architecture characterization for system level performance analysis (DD, AD, ALSV), pp. 734–739.
DATEDATE-2006-OmanaCRM #detection #fault #low cost #reliability
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects (MO, JMC, DR, CM), pp. 170–175.
DATEDATE-2006-PanainteBV #compilation #configuration management
Compiler-driven FPGA-area allocation for reconfigurable computing (EMP, KB, SV), pp. 369–374.
DATEDATE-DF-2006-ArifinC #adaptation #clustering #implementation #logic #novel #segmentation
A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation (SA, PYKC), pp. 227–232.
DATEDATE-DF-2006-HuttonYSBCCP #synthesis #verification
A methodology for FPGA to structured-ASIC synthesis and verification (MH, RY, JS, GB, SC, KKC, HKP), pp. 64–69.
DATEDATE-DF-2006-KappenN #implementation
Application specific instruction processor based implementation of a GNSS receiver on an FPGA (GK, TGN), pp. 58–63.
DATEDATE-DF-2006-LinHJC #optimisation #pattern matching #regular expression
Optimization of regular expression pattern matching circuits on FPGA (CHL, CTH, CPJ, SCC), pp. 12–17.
DATEDATE-DF-2006-MeijerKB #design #energy
Energy-efficient FPGA interconnect design (MM, RK, MTB), pp. 42–47.
DATEDATE-DF-2006-RaabeHAZ #detection #prototype
Space-efficient FPGA-accelerated collision detection for virtual prototyping (AR, SH, JKA, GZ), pp. 206–211.
DATEDATE-DF-2006-VeredasSP #automation #performance
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time (FJV, MS, HJP), pp. 36–41.
LCTESLCTES-2006-YanSG #architecture #configuration management #estimation #implementation
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures (LY, TS, NG), pp. 182–188.
DACDAC-2005-BhattM #design #development #matlab
Matlab as a development environment for FPGA design (TMB, DM), pp. 607–610.
DACDAC-2005-ChengWLLH #architecture #reduction
Device and architecture co-optimization for FPGA power reduction (LC, PW, FL, YL, LH), pp. 915–920.
DACDAC-2005-EguroHS #adaptation #architecture
Architecture-adaptive range limit windowing for simulated annealing FPGA placement (KE, SH, AS), pp. 439–444.
DACDAC-2005-GayasenVI
Exploring technology alternatives for nano-scale FPGA interconnects (AG, NV, MJI), pp. 921–926.
DACDAC-2005-HeitheckerE #requirements
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements (SH, RE), pp. 575–578.
DACDAC-2005-LingSB #case study
FPGA technology mapping: a study of optimality (ACL, DPS, SDB), pp. 427–432.
DACDAC-2005-LinH #performance #reduction
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction (YL, LH), pp. 720–725.
DACDAC-2005-MetzgenN #implementation #multi #reduction
Multiplexer restructuring for FPGA implementation cost reduction (PM, DN), pp. 421–426.
DACDAC-2005-SinghMB #incremental #physics #synthesis
Incremental retiming for FPGA physical synthesis (DPS, VM, SDB), pp. 433–438.
DATEDATE-2005-ChappellMPOFS #adaptation #generative #realtime #safety
Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety Systems (SC, AM, DP, DO, BF, CS), pp. 180–185.
DATEDATE-2005-FaroukS #algorithm #communication #encryption #hybrid #implementation #security
An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security (HAF, MS), pp. 76–81.
DATEDATE-2005-HuotDFR #architecture #logic #multi
FPGA Architecture for Multi-Style Asynchronous Logic (NH, HD, LF, MR), pp. 32–33.
DATEDATE-2005-LyseckyV #case study #clustering #hardware #using
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning (RLL, FV), pp. 18–23.
DATEDATE-2005-PradeepVBK #agile #on-demand
FPGA based Agile Algorithm-On-Demand Co-Processor (RP, SV, SB, VK), pp. 82–83.
DATEDATE-2005-StittV #approach #clustering #decompiler
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms (GS, FV), pp. 396–397.
ICSTSAT-2005-LingSB #logic #quantifier #satisfiability #synthesis #using
FPGA Logic Synthesis Using Quantified Boolean Satisfiability (ACL, DPS, SDB), pp. 444–450.
DACDAC-2004-BrandoleseFS #design #estimation
An area estimation methodology for FPGA based designs at systemc-level (CB, WF, FS), pp. 129–132.
DACDAC-2004-HandaV #algorithm #online #performance
An efficient algorithm for finding empty space for online FPGA placement (MH, RV), pp. 960–965.
DACDAC-2004-KulkarniBS #domain-specific language #framework
Mapping a domain specific language to a platform FPGA (CK, GJB, GS), pp. 924–927.
DACDAC-2004-LiLH #configuration management #reduction #using
FPGA power reduction using configurable dual-Vdd (FL, YL, LH), pp. 735–740.
DACDAC-2004-LyseckyVT #compilation
Dynamic FPGA routing for just-in-time FPGA compilation (RLL, FV, SXDT), pp. 954–959.
DACDAC-2004-NakamuraHKYY #c #c++ #communication #hardware #performance #using
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication (YN, KH, IK, KY, TY), pp. 299–304.
DACDAC-2004-RoyB #algorithm #design #fixpoint #float #matlab
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design (SR, PB), pp. 484–487.
DATEDATE-DF-2004-FaroukS #architecture #design #implementation
Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA (HAF, MS), pp. 212–217.
DATEDATE-DF-2004-FerrerGFAC #implementation #logic #named #network #programmable
NeuroFPGA — Implementing Artificial Neural Networks on Programmable Logic Devices (DF, RG, RF, JPA, RC), pp. 218–223.
DATEDATE-DF-2004-PortoA #2d #architecture #implementation
Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation (RECP, LVA), pp. 224–229.
DATEDATE-v1-2004-BellatoBBCCPRRVZ #memory management
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA (MB, PB, DB, AC, MC, AP, MR, MSR, MV, PZ), pp. 584–589.
DATEDATE-v1-2004-ChenKS #process #scheduling
Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms (GC, MTK, US), pp. 486–493.
DATEDATE-v1-2004-HandaV #algorithm #performance
A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement (MH, RV), pp. 744–745.
DATEDATE-v1-2004-TiriV #design #implementation #logic
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation (KT, IV), pp. 246–251.
ICPRICPR-v1-2004-BariamisIMK #architecture #feature model #image #realtime
An FPGA-Based Architecture for Real Time Image Feature Extraction (DGB, DKI, DEM, SAK), pp. 801–804.
ICPRICPR-v1-2004-JorgLN #realtime #visual notation
FPGA based Real-Time Visual Servoing (SJ, JL, MN), pp. 749–753.
DACDAC-2003-BeraudoL #logic #optimisation #replication
Timing optimization of FPGA placements by logic replication (GB, JL), pp. 196–201.
DACDAC-2003-BorgattiCSFILMPPR #configuration management #embedded #memory management #multi
A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory (MB, LC, GDS, BF, DI, FL, GM, MP, MP, PLR), pp. 691–695.
DACDAC-2003-Tahoori #satisfiability #testing #using
Using satisfiability in application-dependent testing of FPGA interconnects (MBT), pp. 678–681.
DACDAC-2003-YehM
Delay budgeting in sequential circuit with application on FPGA placement (CYY, MMS), pp. 202–207.
DACDAC-2003-ZieglerHD #communication #pipes and filters
Compiler-generated communication for pipelined FPGA applications (HEZ, MWH, PCD), pp. 610–615.
DATEDATE-2003-MazzeoRSM #implementation
FPGA-Based Implementation of a Serial RSA Processor (AM, LR, GPS, NM), pp. 10582–10589.
DATEDATE-2003-VerderberZL #implementation #optimisation #video
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder (MV, AZ, DL), pp. 20238–20243.
DACDAC-2002-ChenMB #configuration management #generative
A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator (JC, JM, KB), pp. 349–354.
DACDAC-2002-HortaLTP #configuration management #hardware #plugin #runtime
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration (ELH, JWL, DET, DBP), pp. 343–348.
DATEDATE-2002-GuccioneVB #configuration management #design
Design Technology for Networked Reconfigurable FPGA Platforms (SG, DV, IB), pp. 994–997.
DATEDATE-2002-VicenteLH #combinator #optimisation
FPGA Placement by Thermodynamic Combinatorial Optimization (JdV, JL, RH), pp. 54–60.
PLDIPLDI-2002-SoHD #approach #compilation #design #hardware #performance
A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems (BS, MWH, PCD), pp. 165–176.
DACDAC-2001-CongR #clustering #multi
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping (JC, MR), pp. 389–394.
DATEDATE-2001-FeketeKT #constraints #precedence
Optimal FPGA module placement with temporal precedence constraints (SPF, EK, JT), pp. 658–667.
DATEDATE-2001-OuaissV #configuration management #memory management #synthesis
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers (IO, RV), pp. 650–657.
DACDAC-2000-HarrisT #architecture #clustering #testing
Interconnect testing in cluster-based FPGA architectures (IGH, RT), pp. 49–54.
DACDAC-2000-HutchingsN #design #programming language #using
Using general-purpose programming languages for FPGA design (BLH, BEN), pp. 561–566.
DACDAC-2000-LachMP #debugging #detection #fault #locality #performance
Efficient error detection, localization, and correction for FPGA-based debugging (JL, WHMS, MP), pp. 207–212.
DATEDATE-2000-BringmannRM #architecture #multi #synthesis
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation (OB, WR, CM), pp. 326–332.
DACDAC-1999-KaulVGO #approach #automation #clustering #configuration management #synthesis
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications (MK, RV, SG, IO), pp. 616–622.
DACDAC-1999-LachMP #multi #robust
Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks (JL, WHMS, MP), pp. 831–836.
DACDAC-1999-ZhuL #compilation #configuration management #hardware
Hardware Compilation for FPGA-Based Configurable Computing Machines (XZ, BL), pp. 697–702.
DATEDATE-1999-RenovellPFZ #configuration management #interface #logic #testing
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s (MR, JMP, JF, YZ), pp. 618–622.
DACDAC-1998-CongW #performance
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation (JC, CW), pp. 330–335.
DACDAC-1998-FangW #clustering #functional #multi #replication #using
Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication (WJF, ACHW), pp. 283–286.
DACDAC-1998-HwangCH #approach #design #power management #re-engineering #using
A Re-engineering Approach to Low Power FPGA Design Using SPFD (JMH, FYC, TH), pp. 722–725.
DACDAC-1998-JiangJH #composition #encoding #synthesis
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis (JHRJ, JYJ, JDH), pp. 712–717.
DACDAC-1998-KorupoluLW #independence #logic
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs (MRK, KKL, DFW), pp. 708–711.
DATEDATE-1998-MartinR
A Comparing Study of Technology Mapping for FPGA (HGM, WR), pp. 939–940.
DATEDATE-1998-RenovellPFZ #approach #configuration management #logic
RAM-Based FPGA’s: A Test Approach for the Configurable Logic (MR, JMP, JF, YZ), pp. 82–88.
DATEDATE-1998-RunjeK #encryption #implementation
Universal Strong Encryption FPGA Core Implementation (DR, MK), pp. 923–924.
DATEDATE-1998-XuK #architecture #synthesis
Layout-Driven High Level Synthesis for FPGA Based Architectures (MX, FJK), pp. 446–450.
HPCAHPCA-1998-AbramsonLPR #problem
FPGA Based Custom Computing Machines for Irregular Problems (DA, PL, AP, MR), pp. 324–333.
DACDAC-1997-AdeLP #data flow #graph #memory management
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets (MA, RL, JAP), pp. 64–69.
DACDAC-1997-ChenHL #approach #design #power management #re-engineering
Low Power FPGA Design — A Re-engineering Approach (CSC, TH, CLL), pp. 656–661.
DACDAC-1997-CongW #pipes and filters #synthesis
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (JC, CW), pp. 644–649.
DACDAC-1997-FangW #clustering #design #multi
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy (WJF, ACHW), pp. 518–521.
DACDAC-1997-KrupnovaAS #clustering
A Hierarchy-Driven FPGA Partitioning Method (HK, AA, GS), pp. 522–525.
DACDAC-1996-CongH #composition #design
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design (JC, YYH), pp. 726–729.
DACDAC-1996-Koch
Module Compaction in FPGA-based Regular Datapaths (AK), pp. 471–476.
DACDAC-1996-LeglWE #approach #design
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs (CL, BW, KE), pp. 730–733.
DACDAC-1996-PanL
Optimal Clock Period FPGA Technology Mapping for Sequential Circuits (PP, CLL), pp. 720–725.
DACDAC-1995-AlexanderR #algorithm
New Performance-Driven FPGA Routing Algorithms (MJA, GR), pp. 562–567.
DACDAC-1995-MakW #logic #on the
On Optimal Board-Level Routing for FPGA-Based Logic Emulation (WKM, DFW), pp. 552–556.
DACDAC-1995-ShenHC #composition #set
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping (WZS, JDH, SMC), pp. 65–69.
DACDAC-1995-StanionS #synthesis
A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis (TS, CS), pp. 60–64.
DACDAC-1995-Trimberger #architecture
Effects of FPGA Architecture on FPGA Routing (ST), pp. 574–578.
DACDAC-1995-WuM #2d #approach #optimisation #orthogonal
Orthogonal Greedy Coupling — A New Optimization Approach to 2-D FPGA Routing (YLW, MMS), pp. 568–573.
DACDAC-1994-SunL #2d #architecture
Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture (YS, CLL), pp. 171–176.
DACDAC-1994-ZhuW94a
Clock Skew Minimization During FPGA Placement (KZ, DFW), pp. 232–237.
DATEEDAC-1994-BrasenS #clustering
FPGA Partitioning for Critical Paths (DRB, GS), pp. 99–103.
DACDAC-1993-CongD #on the #trade-off
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping (JC, YD), pp. 213–218.
DACDAC-1993-LaiPV #composition #logic #synthesis
BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis (YTL, MP, SBKV), pp. 642–647.
DACDAC-1993-WooK #clustering #implementation #multi #performance
An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation. (NSW, JK), pp. 202–207.
DACDAC-1992-ChungR #architecture #named
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections (KC, JR), pp. 361–367.
DACDAC-1992-Frankle #adaptation #layout
Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing (JF), pp. 536–542.
DACDAC-1992-HillD #design #tutorial
FPGA Design Principles (A Tutorial) (DDH, ED), pp. 45–46.
DACDAC-1992-SchlichtmannBH #agile
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping (US, FB, MH), pp. 374–379.
DACDAC-1991-Woo #heuristic
A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility (NSW), pp. 248–251.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.