*Proceedings of the 40th Design Automation Conference*

DAC, 2003.

@proceedings{DAC-2003, acmid = "775832", address = "Anaheim, California, USA", isbn = "1-58113-688-9", publisher = "{ACM}", title = "{Proceedings of the 40th Design Automation Conference}", year = 2003, }

### Contents (189 items)

- DAC-2003-Schubert #verification
- High level formal verification of next-generation microprocessors (TS), pp. 1–6.
- DAC-2003-MathysC #integration #verification
- Verification strategy for integration 3G baseband SoC (YM, AC), pp. 7–10.
- DAC-2003-Schubert03a #challenge #distributed #functional #industrial #scalability #simulation
- Improvements in functional simulation addressing challenges in large, distributed industry projects (KDS), pp. 11–14.
- DAC-2003-RabaeySBBFHNSY
- Reshaping EDA for power (JMR, DS, DB, KB, JF, MH, WN, TS, AY), p. 15.
- DAC-2003-GuptaKSY #off the shelf #tool support
- A cost-driven lithographic correction methodology based on off-the-shelf sizing tools (PG, ABK, DS, JY), pp. 16–21.
- DAC-2003-ChenGK #synthesis
- Performance-impact limited area fill synthesis (YC, PG, ABK), pp. 22–27.
- DAC-2003-HadsellM #estimation
- Improved global routing through congestion estimation (RH, PHM), pp. 28–31.
- DAC-2003-CongJRR #architecture #evaluation #physics
- Microarchitecture evaluation with physical planning (JC, AJ, GR, MR), pp. 32–35.
- DAC-2003-BeniniMMOPP #analysis #design #difference #energy
- Energy-aware design techniques for differential power analysis protection (LB, AM, EM, EO, FP, MP), pp. 36–41.
- DAC-2003-FummiPGPMR #embedded #modelling #simulation
- A timing-accurate modeling and simulation environment for networked embedded systems (FF, GP, PG, MP, SM, FR), pp. 42–47.
- DAC-2003-DamaseviciusMS #design pattern #hardware
- Application of design patterns for hardware design (RD, GM, VS), pp. 48–53.
- DAC-2003-KornarosPNZ #memory management #multi #optimisation #programmable #queue
- A fully-programmable memory management system optimizing queue handling at multi-gigabit rates (GK, IP, AN, NZ), pp. 54–59.
- DAC-2003-HwangLSSFYHV #design #embedded
- Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system (DDH, BCL, PS, KS, YF, SY, AH, IV), pp. 60–65.
- DAC-2003-WongMP #case study #design
- Design techniques for sensor appliances: foundations and light compass case study (JLW, SM, MP), pp. 66–71.
- DAC-2003-Barkai #challenge #integration #multi
- Seamless multi-radio integration challenges (UB), p. 72.
- DAC-2003-Hooijmans #roadmap
- RF front end application and technology trends (PWH), pp. 73–78.
- DAC-2003-CraninckxD #design #how #question
- 4G terminals: how are we going to design them? (JC, SD), pp. 79–84.
- DAC-2003-RootWT #behaviour #metric #modelling #simulation
- New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurements (DER, JW, NT), pp. 85–90.
- DAC-2003-DahlbergRBGKPRSV #named
- COT — customer owned trouble (RD, SR, JB, GG, AK, KP, PR, NAS, RV), pp. 91–92.
- DAC-2003-QianNS #network #random
- Random walks in a supply network (HQ, SRN, SSS), pp. 93–98.
- DAC-2003-KouroussisN #grid #independence #power management #verification
- A static pattern-independent technique for power grid voltage integrity verification (DK, FNN), pp. 99–104.
- DAC-2003-ZhuYC #adaptation #algebra #analysis #approach #multi #network #using
- Power network analysis using an adaptive algebraic multigrid approach (ZZ, BY, CKC), pp. 105–108.
- DAC-2003-SuAN #algebra #grid #multi #power management #reduction
- Power grid reduction based on algebraic multigrid principles (HS, EA, SRN), pp. 109–112.
- DAC-2003-WangM #multi #network #optimisation #power management #using
- On-chip power supply network optimization using multigrid-based technique (KW, MMS), pp. 113–118.
- DAC-2003-LiXC #architecture #modelling #optimisation #power management #scalability
- Scalable modeling and optimization of mode transitions based on decoupled power management architecture (DL, QX, PHC), pp. 119–124.
- DAC-2003-KwonK
- Optimal voltage allocation techniques for dynamically variable voltage processors (WCK, TK), pp. 125–130.
- DAC-2003-HuaQB #energy #multi #reduction
- Energy reduction techniques for multimedia applications with tolerance to deadline misses (SH, GQ, SSB), pp. 131–136.
- DAC-2003-RamachandranJ #embedded #energy #memory management #named #performance
- Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing (AR, MFJ), pp. 137–142.
- DAC-2003-MishchenkoWK #algorithm #composition
- A new enhanced constructive decomposition and mapping algorithm (AM, XW, TK), pp. 143–148.
- DAC-2003-MishchenkoS #composition #functional #scalability #using
- Large-scale SOP minimization using decomposition and functional properties (AM, TS), pp. 149–154.
- DAC-2003-JiangMB #evaluation #logic
- Generalized cofactoring for logic function evaluation (YJ, SM, RKB), pp. 155–158.
- DAC-2003-Edwards
- Making cyclic circuits acyclic (SAE), pp. 159–162.
- DAC-2003-RiedelB #synthesis
- The synthesis of cyclic combinational circuits (MDR, JB), pp. 163–168.
- DAC-2003-MukhopadhyayRR #estimation #logic #modelling
- Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling (SM, AR, KR), pp. 169–174.
- DAC-2003-LeeKBS #analysis
- Analysis and minimization techniques for total leakage considering gate oxide leakage (DL, WK, DB, DS), pp. 175–180.
- DAC-2003-LongH #distributed #network #reduction
- Distributed sleep transistor network for power reduction (CL, LH), pp. 181–186.
- DAC-2003-TsaiDVI #reduction #scalability
- Implications of technology scaling on leakage reduction techniques (YFT, DD, NV, MJI), pp. 187–190.
- DAC-2003-LeeB #reduction
- Static leakage reduction through simultaneous threshold voltage and state assignment (DL, DB), pp. 191–194.
- DAC-2003-ChanHPSMVW #design
- Emerging markets: design goes global (CFC, DH, JYP, NVS, MM, AV, SW), p. 195.
- DAC-2003-BeraudoL #logic #optimisation #replication
- Timing optimization of FPGA placements by logic replication (GB, JL), pp. 196–201.
- DAC-2003-YehM
- Delay budgeting in sequential circuit with application on FPGA placement (CYY, MMS), pp. 202–207.
- DAC-2003-CongY #multi
- Multilevel global placement with retiming (JC, XY), pp. 208–213.
- DAC-2003-HurCRPCTH #constraints #physics
- Force directed mongrel with physical net constraints (SWH, TC, KR, YP, AC, VT, BH), pp. 214–219.
- DAC-2003-QinC #reduction #using
- Realizable parasitic reduction using generalized Y-Delta transformation (ZQ, CKC), pp. 220–225.
- DAC-2003-AminCI
- Realizable RLCK circuit crunching (CSA, MHC, YII), pp. 226–231.
- DAC-2003-MeiAI #order #performance #reduction
- Efficient model order reduction including skin effect (SM, CSA, YII), pp. 232–237.
- DAC-2003-GadN #congruence #order #reduction #using
- Model order reduction of nonuniform transmission lines using integrated congruence transform (EG, MSN), pp. 238–243.
- DAC-2003-SzymanekK #constraints #graph
- Partial task assignment of task graphs under heterogeneous resource constraints (RS, KK), pp. 244–249.
- DAC-2003-StittLV #approach #clustering #hardware
- Dynamic hardware/software partitioning: a first approach (GS, RLL, FV), pp. 250–255.
- DAC-2003-AtasuPI #architecture #automation #constraints
- Automatic application-specific instruction-set extensions under microarchitectural constraints (KA, LP, PI), pp. 256–261.
- DAC-2003-NohlGBALSM #architecture #encoding #modelling #synthesis #using
- Instruction encoding synthesis for architecture exploration using hierarchical processor models (AN, VG, GB, AH, RL, OS, HM), pp. 262–267.
- DAC-2003-Bernstein #automaton
- Quantum-dot cellular automata: computing by field polarization (GHB), pp. 268–273.
- DAC-2003-Wasshuber
- Recent advances and future prospects in single-electronics (CW), pp. 274–275.
- DAC-2003-AmlaniZTNT #component
- Manipulation and characterization of molecular scale components (IA, RZ, JT, LN, RKT), pp. 276–277.
- DAC-2003-RutenbarHJKMRS
- Mixed signals on mixed-signal: the right next technology (RAR, DLH, KJ, PK, THYM, RR, JS), pp. 278–279.
- DAC-2003-Gluska #verification
- Coverage-oriented verification of banias (AG), pp. 280–285.
- DAC-2003-FineZ #functional #generative #network #testing #using #verification
- Coverage directed test generation for functional verification using bayesian networks (SF, AZ), pp. 286–291.
- DAC-2003-JayakumarPS #estimation
- Dos and don’ts of CTL state coverage estimation (NJ, MP, FS), pp. 292–295.
- DAC-2003-YuanAAP #constraints #functional #modelling #synthesis #verification
- Constraint synthesis for environment modeling in functional verification (JY, KA, AA, CP), pp. 296–299.
- DAC-2003-AbdiSG #automation #communication #design #refinement
- Automatic communication refinement for system level design (SA, DS, DG), pp. 300–305.
- DAC-2003-LekatsasHCJS #agile #framework #hardware #named #platform #prototype
- CoCo: a hardware/software platform for rapid prototyping of code compression technologies (HL, JH, STC, VJ, MS), pp. 306–311.
- DAC-2003-MeyerowitzPS #policy #realtime #scheduling
- A tool for describing and evaluating hierarchical real-time bus scheduling policies (TM, CP, ALSV), pp. 312–317.
- DAC-2003-MillerMD #algorithm #logic #synthesis
- A transformation based algorithm for reversible logic synthesis (DMM, DM, GWD), pp. 318–323.
- DAC-2003-BullockM
- An arbitrary twoqubit computation In 23 elementary gates or less (SSB, ILM), pp. 324–329.
- DAC-2003-SaifhashemiP #abstraction #framework #modelling
- Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction (AS, HP), pp. 330–333.
- DAC-2003-LyseckyV #logic
- On-chip logic minimization (RLL, FV), pp. 334–337.
- DAC-2003-BorkarKNTKD #architecture #parametricity
- Parameter variations and impact on circuits and microarchitecture (SB, TK, SN, JT, AK, VD), pp. 338–342.
- DAC-2003-Visweswariah
- Death, taxes and failing chips (CV), pp. 343–347.
- DAC-2003-AgarwalBZV #bound #refinement #statistics
- Computation and Refinement of Statistical Bounds on Circuit Delay (AA, DB, VZ, SBKV), pp. 348–353.
- DAC-2003-El-GamalBBHMOP #implementation #performance
- Fast, cheap and under control: the next implementation fabric (AEG, IB, AB, CH, PM, ZOB, LTP), pp. 354–355.
- DAC-2003-TasiranYB #model checking #monitoring #simulation #specification #using
- Using a formal specification and a model checker to monitor and direct simulation (ST, YY, BB), pp. 356–361.
- DAC-2003-HsuTCT #debugging
- Advanced techniques for RTL debugging (YCH, BT, YAC, FST), pp. 362–367.
- DAC-2003-ClarkeKY #behaviour #bound #c #consistency #model checking #source code #using
- Behavioral consistency of C and verilog programs using bounded model checking (EMC, DK, KY), pp. 368–371.
- DAC-2003-HenftlingZBZE #architecture
- Re-use-centric architecture for a fully accelerated testbench environment (RH, AZ, MB, MZ, WE), pp. 372–375.
- DAC-2003-AgarwalSB #effectiveness
- An effective capacitance based driver output model for on-chip RLC interconnects (KA, DS, DB), pp. 376–381.
- DAC-2003-AlpertLKD #metric #using
- Delay and slew metrics using the lognormal distribution (CJA, FL, CVK, AD), pp. 382–385.
- DAC-2003-CroixW #analysis #modelling #using
- Blade and razor: cell and interconnect delay analysis using current-based models (JFC, DFW), pp. 386–389.
- DAC-2003-ThudiB
- Non-iterative switching window computation for delay-noise (BT, DB), pp. 390–395.
- DAC-2003-RussellJ #architecture #component #embedded #evaluation #performance
- Architecture-level performance evaluation of component-based embedded systems (JTR, MFJ), pp. 396–401.
- DAC-2003-PimentelE #communication #refinement
- An IDF-based trace transformation method for communication refinement (ADP, CE), pp. 402–407.
- DAC-2003-PaulBNPT #design #modelling #multi #programmable
- Schedulers as model-based design elements in programmable heterogeneous multiprocessors (JMP, AB, JEN, JJP, DET), pp. 408–411.
- DAC-2003-KiranJRN #behaviour #communication #complexity #effectiveness #modelling
- A complexity effective communication model for behavioral modeling of signal processing applications (MNVSK, MNJ, PR, SKN), pp. 412–415.
- DAC-2003-Spirakis #challenge #design #question
- Leading-edge and future design challenges — is the classical EDA ready? (GS), p. 416.
- DAC-2003-Matsuzawa #collaboration #communication #how #optimisation #performance
- How to make efficient communication, collaboration, and optimization from system to chip (AM), pp. 417–418.
- DAC-2003-MagarshackP
- System-on-chip beyond the nanometer wall (PM, PGP), pp. 419–424.
- DAC-2003-SeshiaLB #hybrid #logic #satisfiability
- A hybrid SAT-based decision procedure for separation logic with uninterpreted functions (SAS, SKL, REB), pp. 425–430.
- DAC-2003-GoelHB #order #representation
- Symbolic representation with ordered function templates (AG, GH, REB), pp. 431–435.
- DAC-2003-LuWCMH #case study #correlation #industrial
- A signal correlation guided ATPG solver and its applications for solving difficult industrial cases (FL, LCW, KTC, JM, ZH), pp. 436–441.
- DAC-2003-NgPMJ #industrial #problem
- Solving the latch mapping problem in an industrial setting (KN, MRP, RM, JJ), pp. 442–447.
- DAC-2003-AgostaBS #modelling #static analysis #transaction
- Static analysis of transaction-level models (GA, FB, DS), pp. 448–453.
- DAC-2003-JersakE #analysis #dependence #multi #scheduling
- Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals (MJ, RE), pp. 454–459.
- DAC-2003-ChenHBW #analysis #automation #constraints #logic
- Automatic trace analysis for logic of constraints (XC, HH, FB, YW), pp. 460–465.
- DAC-2003-LiMR #analysis #interactive #modelling
- Accurate timing analysis by modeling caches, speculation and their interaction (XL, TM, AR), pp. 466–471.
- DAC-2003-LiP #named #order #reduction
- NORM: compact model order reduction of weakly nonlinear systems (PL, LTP), pp. 472–477.
- DAC-2003-LiLXP #analysis #megamodelling
- Analog and RF circuit macromodels for system-level analysis (XL, PL, YX, LTP), pp. 478–483.
- DAC-2003-DongR #polynomial #reduction
- Piecewise polynomial nonlinear model reduction (ND, JSR), pp. 484–489.
- DAC-2003-VasilyevRW #algorithm #generative #modelling
- A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS (DV, MR, JW), pp. 490–495.
- DAC-2003-FangRPC #modelling #performance #static analysis #towards
- Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling (CFF, RAR, MP, TC), pp. 496–501.
- DAC-2003-AmdeBS #automation #design
- Automating the design of an asynchronous DLX microprocessor (MA, IB, CPS), pp. 502–507.
- DAC-2003-WongM #composition #data-driven #synthesis
- High-level synthesis of asynchronous systems by data-driven decomposition (CGW, AJM), pp. 508–513.
- DAC-2003-SoDH #behaviour #design #synthesis #tool support #using
- Using estimates from behavioral synthesis tools in compiler-directed design space exploration (BS, PCD, MWH), pp. 514–519.
- DAC-2003-SengerMMGKGB
- A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference (RMS, EDM, MSM, FHG, KLK, MRG, RBB), pp. 520–525.
- DAC-2003-LauP #algorithm #design #using
- Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm (CYL, MHP), pp. 526–531.
- DAC-2003-Heydari
- Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators (PH), pp. 532–537.
- DAC-2003-VasudevanR #using
- Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique (VV, MR), pp. 538–541.
- DAC-2003-MantheLS #analysis
- Symbolic analysis of analog circuits with hard nonlinearity (AM, ZL, CJRS), pp. 542–545.
- DAC-2003-KahngBCDGSS #design
- Nanometer design: place your bets (ABK, SB, JMC, AD, PG, LS, JPS), pp. 546–547.
- DAC-2003-ChenRRD #programmable #scalability #self
- A scalable software-based self-test methodology for programmable processors (LC, SR, AR, SD), pp. 548–553.
- DAC-2003-LiYRP #generative #markov #using
- A scan BIST generation method using a markov source and partial bit-fixing (WL, CY, SMR, IP), pp. 554–559.
- DAC-2003-Al-YamaniM #automaton #encoding
- Seed encoding with LFSRs and cellular automata (AAAY, EJM), pp. 560–565.
- DAC-2003-WohlWPA #architecture #logic #performance
- Efficient compression and application of deterministic patterns in a logic BIST architecture (PW, JAW, SP, MBA), pp. 566–569.
- DAC-2003-NegreirosCS #low cost
- Ultimate low cost analog BIST (MN, LC, AAS), pp. 570–573.
- DAC-2003-HuWKM #library
- Gain-based technology mapping for discrete-size cell libraries (BH, YW, AK, MMS), pp. 574–579.
- DAC-2003-ShiL #algorithm
- An O(nlogn) time algorithm for optimal buffer insertion (WS, ZL), pp. 580–585.
- DAC-2003-GhoneimaI #bidirectional
- Optimum positioning of interleaved repeaters In bidirectional buses (MG, YII), pp. 586–591.
- DAC-2003-RenG #performance
- Synthesizing optimal filters for crosstalk-cancellation for high-speed buses (JR, MRG), pp. 592–597.
- DAC-2003-MaideeAB #clustering #performance
- Fast timing-driven partitioning-based placement for island style FPGAs (PM, CA, KB), pp. 598–603.
- DAC-2003-MemikMJK #data flow #graph #resource management #synthesis
- Global resource sharing for synthesis of control data flow graphs on FPGAs (SOM, GM, RJ, EK), pp. 604–609.
- DAC-2003-ZieglerHD #communication #pipes and filters
- Compiler-generated communication for pipelined FPGA applications (HEZ, MWH, PCD), pp. 610–615.
- DAC-2003-KaplanBK #communication #configuration management #estimation #reduction
- Data communication estimation and reduction for reconfigurable systems (AK, PB, RK), pp. 616–621.
- DAC-2003-DonnoIBM #optimisation
- Clock-tree power optimization based on RTL clock-gating (MD, AI, LB, EM), pp. 622–627.
- DAC-2003-BashirullahLC #adaptation #design #power management
- Low-power design methodology for an on-chip bus with adaptive bandwidth capability (RB, WL, RKCI), pp. 628–633.
- DAC-2003-MoreshetB #design #power management #queue
- Power-aware issue queue design for speculative instructions (TM, RIB), pp. 634–637.
- DAC-2003-BergamaschiJ #analysis
- State-based power analysis for systems-on-chip (RAB, YJ), pp. 638–641.
- DAC-2003-SechenCHMNNT #library #named
- Libraries: lifejacket or straitjacket (CS, BC, JH, AM, TN, GAN, AT), pp. 642–643.
- DAC-2003-EjlaliM
- Switch-level emulation (ARE, SGM), pp. 644–649.
- DAC-2003-LimaCR #design #fault tolerance
- Designing fault tolerant systems into SRAM-based FPGAs (FL, LC, RAdLR), pp. 650–655.
- DAC-2003-CarlettaVKF #fixpoint
- Determining appropriate precisions for signals in fixed-point IIR filters (JC, RJV, FWK, ZF), pp. 656–661.
- DAC-2003-LinT #design #generative #multi #testing
- Test generation for designs with multiple clocks (XL, RT), pp. 662–667.
- DAC-2003-KrsticWCLM #fault #modelling #statistics
- Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models (AK, LCW, KTC, JJL, TMM), pp. 668–673.
- DAC-2003-HuangC #embedded #framework #using #verification
- Using embedded infrastructure IP for SOC post-silicon verification (YH, WTC), pp. 674–677.
- DAC-2003-Tahoori #satisfiability #testing #using
- Using satisfiability in application-dependent testing of FPGA interconnects (MBT), pp. 678–681.
- DAC-2003-OMahonyYHW #design #network #using
- Design of a 10GHz clock distribution network using coupled standing-wave oscillators (FO, CPY, MH, SSW), pp. 682–687.
- DAC-2003-ManeatisKMMS #generative #multi #self
- Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL (JGM, JK, IM, JM, MS), pp. 688–690.
- DAC-2003-BorgattiCSFILMPPR #configuration management #embedded #memory management #multi
- A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory (MB, LC, GDS, BF, DI, FL, GM, MP, MP, PLR), pp. 691–695.
- DAC-2003-ChanKLNR #performance #physics #synthesis
- Physical synthesis methodology for high performance microprocessors (YHC, PK, LBL, GAN, TER), pp. 696–701.
- DAC-2003-AndoYISAMMMOYSKYS #generative
- A 1.3GHz fifth generation SPARC64 microprocessor (HA, YY, AI, IS, TA, KM, TM, TM, SO, HY, YS, AK, RY, HS), pp. 702–705.
- DAC-2003-StinsonR #generative
- A 1.5GHz third generation itanium® 2 processor (JS, SR), pp. 706–709.
- DAC-2003-GuptaRSBBFPOS #verification
- Formal verification — prove it or pitch it (RKG, SR, SKS, BB, DKB, MF, CP, JO, FS), pp. 710–711.
- DAC-2003-ZhuSW #3d #algorithm #geometry #performance
- Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometries (ZZ, BS, JW), pp. 712–717.
- DAC-2003-YuH
- Vector potential equivalent circuit based on PEEC inversion (HY, LH), pp. 718–723.
- DAC-2003-GorenZGWBALSTGPJSSDH #design #modelling
- On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices (DG, MZ, RG, IAW, AB, AA, BL, AS, YT, RAG, JP, DLJ, SES, RS, CED, DLH), pp. 724–727.
- DAC-2003-ZhongKBR #adaptation #implementation #performance
- An adaptive window-based susceptance extraction and its efficient implementation (GZ, CKK, VB, KR), pp. 728–731.
- DAC-2003-RaoBO
- Test application time and volume compression through seed overlapping (WR, IB, AO), pp. 732–737.
- DAC-2003-SehgalIKC #multi #reduction #using
- Test cost reduction for SOCs using virtual TAMs and lagrange multipliers (AS, VI, MDK, KC), pp. 738–743.
- DAC-2003-XiangGSW #architecture #effectiveness #testing
- A cost-effective scan architecture for scan testing with non-scan test power and test application cost (DX, SG, JGS, YLW), pp. 744–747.
- DAC-2003-PomeranzR #detection #on the #testing
- On test data compression and n-detection test sets (IP, SMR), pp. 748–751.
- DAC-2003-MongZ #architecture
- A retargetable micro-architecture simulator (WSM, JZ), pp. 752–757.
- DAC-2003-ReshadiMD #flexibility #performance #set #simulation
- Instruction set compiled simulation: a technique for fast and flexible instruction set simulation (MR, PM, NDD), pp. 758–763.
- DAC-2003-QinM #automation #performance #synthesis
- Automated synthesis of efficient binary decoders for retargetable software toolkits (WQ, SM), pp. 764–769.
- DAC-2003-LackeyZK #design
- Designing mega-ASICs in nanogate technologies (DEL, PSZ, JK), pp. 770–775.
- DAC-2003-BittlestoneHSA #architecture #library
- Architecting ASIC libraries and flows in nanometer era (CB, AMH, VS, NVA), pp. 776–781.
- DAC-2003-PileggiSSGKKPRT #trade-off
- Exploring regular fabrics to optimize the performance-cost trade-off (LTP, HS, AJS, PG, VK, AK, CP, VR, KYT), pp. 782–787.
- DAC-2003-PuriSCKPSSK #performance
- Pushing ASIC performance in a power envelope (RP, LS, JMC, DSK, DZP, DS, AS, SHK), pp. 788–793.
- DAC-2003-ChenCCKMSYZ #algebra #clustering #layout #multi
- An algebraic multigrid solver for analytical placement with layout based clustering (HC, CKC, NCC, ABK, JFM, PS, BY, ZZ), pp. 794–799.
- DAC-2003-HuM #clustering #predict
- Wire length prediction based clustering and its application in placement (BH, MMS), pp. 800–805.
- DAC-2003-MaHDCCCG #analysis #optimisation
- Dynamic global buffer planning optimization based on detail block locating and congestion analysis (YM, XH, SD, SC, YC, CKC, JG), pp. 806–811.
- DAC-2003-LeeCHY #multi #scalability #using
- Multilevel floorplanning/placement for large-scale modules using B*-trees (HCL, YWC, JMH, HHY), pp. 812–817.
- DAC-2003-DamianoK #satisfiability
- Checking satisfiability of a conjunction of BDDs (RFD, JHK), pp. 818–823.
- DAC-2003-GuptaGWYA #bound #learning #model checking #satisfiability
- Learning from BDDs in SAT-based bounded model checking (AG, MKG, CW, ZY, PA), pp. 824–829.
- DAC-2003-ChaiK #constraints #performance #pseudo #theorem proving
- A fast pseudo-boolean constraint solver (DC, AK), pp. 830–835.
- DAC-2003-AloulMS #named #performance #satisfiability #symmetry
- Shatter: efficient symmetry-breaking for boolean satisfiability (FAA, ILM, KAS), pp. 836–839.
- DAC-2003-KangP #bound #model checking #satisfiability
- SAT-based unbounded symbolic model checking (HJK, ICP), pp. 840–843.
- DAC-2003-DescampsBGIP #design #network #using
- Design of a 17-million gate network processor using a design factory (GED, SB, SG, SI, AP), pp. 844–849.
- DAC-2003-ShiG #hybrid #performance #power management
- Hybrid hierarchical timing closure methodology for a high performance and low power DSP (KS, GG), pp. 850–855.
- DAC-2003-FerzliN #estimation #grid #power management #process #statistics
- Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations (IAF, FNN), pp. 856–859.
- DAC-2003-ChaiKRTWM #analysis
- Temporofunctional crosstalk noise analysis (DC, AK, YR, KHT, YW, MMS), pp. 860–863.
- DAC-2003-TsengK #analysis
- Static noise analysis with noise windows (KT, VK), pp. 864–868.
- DAC-2003-JainSD #embedded
- Embedded intelligent SRAM (PJ, GES, SD), pp. 869–874.
- DAC-2003-Givargis #embedded #reduction
- Improved indexing for cache miss reduction in embedded systems (TG), pp. 875–880.
- DAC-2003-ChoiK #design #embedded #layout #memory management #performance
- Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design (YC, TK), pp. 881–886.
- DAC-2003-ZhangCKK #embedded #interprocedural #optimisation #performance
- Interprocedural optimizations for improving data cache performance of array-intensive embedded applications (WZ, GC, MTK, MK), pp. 887–892.
- DAC-2003-Hayes #concept #named #quantum #tutorial
- Tutorial: basic concepts in quantum circuits (JPH), p. 893.
- DAC-2003-Travaglione #algorithm #design #implementation #quantum
- Designing and implementing small quantum circuits and algorithms (BT), pp. 894–899.
- DAC-2003-RaghunathanSG #communication #energy #overview #performance
- A survey of techniques for energy efficient on-chip communication (VR, MBS, RKG), pp. 900–905.
- DAC-2003-RongP #approach #markov #mobile #network
- Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approach (PR, MP), pp. 906–911.
- DAC-2003-ChoiKP #energy #streaming
- Energy-aware MPEG-4 FGS streaming (KC, KK, MP), pp. 912–915.
- DAC-2003-AmmerSKKR #energy
- A low-energy chip-set for wireless intercom (MJA, MS, TCK, MK, JMR), pp. 916–919.
- DAC-2003-BozorgzadehGTS #graph #integer
- Optimal integer delay budgeting on directed acyclic graphs (EB, SG, AT, MS), pp. 920–925.
- DAC-2003-PenryA #component #optimisation #reuse
- Optimizations for a simulator construction system supporting reusable components (DAP, DIA), pp. 926–931.
- DAC-2003-JessKNOV #parametricity #predict #statistics
- Statistical timing for parametric yield prediction of digital integrated circuits (JAGJ, KK, SRN, RHJMO, CV), pp. 932–937.
- DAC-2003-Kumar #design
- Interconnect and noise immunity design for the Pentium 4 processor (RK0), pp. 938–943.
- DAC-2003-RanM
- Crosstalk noise in FPGAs (YR, MMS), pp. 944–949.
- DAC-2003-AgarwalSB03a #metric
- Simple metrics for slew rate of RC circuits based on two circuit moments (KA, DS, DB), pp. 950–953.
- DAC-2003-BecerBAPOZH #reduction
- Post-route gate sizing for crosstalk noise reduction (MRB, DB, IA, RP, CO, VZ, INH), pp. 954–957.
- DAC-2003-StehrGA #analysis #bound #performance #trade-off
- Performance trade-off analysis of analog circuits by normal-boundary intersection (GS, HEG, KA), pp. 958–963.
- DAC-2003-BernardinisJS #performance #representation
- Support vector machines for analog circuit performance representation (FDB, MIJ, ALSV), pp. 964–969.
- DAC-2003-Hershenson #design #performance
- Efficient description of the design space of analog circuits (MdMH), pp. 970–973.
- DAC-2003-VogelsG #architecture
- Architectural selection of A/D converters (MV, GGEG), pp. 974–977.

24 ×#design

24 ×#performance

21 ×#using

16 ×#modelling

15 ×#multi

14 ×#analysis

14 ×#reduction

12 ×#architecture

10 ×#embedded

10 ×#synthesis

24 ×#performance

21 ×#using

16 ×#modelling

15 ×#multi

14 ×#analysis

14 ×#reduction

12 ×#architecture

10 ×#embedded

10 ×#synthesis