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Travelled to:
1 × Germany
Collaborated with:
B.M.Al-Hashimi P.Eles
Talks about:
synthesi (1) schedul (1) system (1) condit (1) power (1) graph (1) embed (1) task (1) map (1) low (1)

Person: Dong Wu

DBLP DBLP: Wu:Dong

Contributed to:

DATE 20032003

Wrote 1 papers:

DATE-2003-WuAE #embedded #graph #power management #scheduling #synthesis
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems (DW, BMAH, PE), pp. 10090–10095.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.