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Travelled to:
1 × Ireland
2 × USA
Collaborated with:
E.L.Leiss E.D.Granston J.Zbiciak
Talks about:
architectur (2) schedul (2) modulo (2) vliw (2) tms (2) dsp (2) irregular (1) without (1) softwar (1) pipelin (1)

Person: Eric Stotzer

DBLP DBLP: Stotzer:Eric

Contributed to:

LCTES 20092009
LCTES/OM 20012001
LCTES 19991999

Wrote 3 papers:

LCTES-2009-StotzerL #scheduling
Modulo scheduling without overlapped lifetimes (ES, ELL), pp. 1–10.
LCTES-OM-2001-GranstonSZ #architecture #pipes and filters
Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture (EDG, ES, JZ), pp. 138–144.
LCTES-1999-StotzerL #architecture #scheduling
Modulo Scheduling for the TMS320C6x VLIW DSP Architecture (ES, ELL), pp. 28–34.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.