Stem vliw$ (all stems)

57 papers:

DATE-2014-ZhangWSX #clustering

Lifetime holes aware register allocation for clustered VLIW processors (XZ, HW, HS, JX), pp. 1–4.

LCTES-2014-LeeLLP #architecture #performance

Improving performance of loops on DIAM-based VLIW architectures (JL, JL, JL, YP), pp. 135–144.

DAC-2013-RahimiBG #architecture

Aging-aware compiler-directed VLIW assignment for GPGPU architectures (AR, LB, RKG), p. 6.

DATE-2013-BrandonW #using

Support for dynamic issue width in VLIW processors using generic binaries (AB, SW), pp. 827–832.

DATE-2012-SabenaRS #algorithm #testing

A new SBST algorithm for testing the register file of VLIW processors (DS, MSR, LS), pp. 412–417.

LCTES-2012-HuangZX #architecture #clustering #embedded #realtime

WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture (YH, MZ, CJX), pp. 31–40.

DATE-2011-BernardC #power management

A low-power VLIW processor for 3GPP-LTE complex numbers processing (CB, FC), pp. 234–239.

DATE-2010-WongAN #configuration management

Dynamically reconfigurable register file for a softcore VLIW processor (SW, FA, FN), pp. 969–972.

DAC-2009-BonnyH #named #performance

LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors (TB, JH), pp. 903–906.

DATE-2007-Scholzel #clustering #interactive

Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP (MS), pp. 467–472.

CGO-2007-AletaCGK #architecture #clustering

Heterogeneous Clustered VLIW Microarchitectures (AA, JMC, AG, DRK), pp. 354–366.

LCTES-2007-ChenTCLYLL #compilation #distributed #embedded

Enabling compiler flow for embedded VLIW DSP processors with distributed register files (CKC, LHT, SCC, YJL, YPY, CHL, JKL), pp. 146–148.

LCTES-2007-XuT #named

Tetris: a new register pressure control technique for VLIW processors (WX, RT), pp. 113–122.

LCTES-2007-YanL #architecture #clustering #execution

Stream execution on wide-issue clustered VLIW architectures (SY, BL), pp. 158–160.

DATE-2006-RaghavanLJCV #architecture #distributed #multi #thread

Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors (PR, AL, MJ, FC, DV), pp. 339–344.

LCTES-2006-MutyamLNKI #functional

Compiler-directed thermal management for VLIW functional units (MM, FL, NV, MTK, MJI), pp. 163–172.

DAC-2005-AdirADLRVCCD #case study #named #parallel #verification

VLIW: a case study of parallelism verification (AA, YA, BD, YL, MR, MV, MAC, AC, GD), pp. 779–782.

DATE-2005-BarrettaFSB #clustering #embedded #parallel #thread

Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications (DB, WF, MS, DB), pp. 748–749.

DATE-2005-GangwarBPK #architecture #clustering #evaluation

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures (AG, MB, PRP, AK), pp. 730–735.

DATE-DF-2004-LinXW #embedded

LZW-Based Code Compression for VLIW Embedded Systems (CHL, YX, WW), pp. 76–81.

DATE-v2-2004-MeiVVL #architecture #case study #configuration management #design #matrix

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study (BM, SV, DV, RL), pp. 1224–1229.

DATE-2003-MaciiMCZ #algorithm #embedded #energy

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors (AM, EM, FC, RZ), pp. 10024–10029.

DATE-2003-PillaiJ #clustering #scheduling

Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling (SP, MFJ), pp. 10422–10427.

CGO-2003-GibertSG #clustering #distributed #memory management #scheduling

Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache (EG, FJS, AG), pp. 193–203.

HPCA-2003-TerechkoTGEC #clustering #communication #modelling

Inter-Cluster Communication Models for Clustered VLIW Processors (AT, ELT, MG, JTJvE, HC), pp. 354–364.

LCTES-2003-KimVKI #adaptation #architecture #optimisation #parallel

Adapting instruction level parallelism for optimizing leakage in VLIW architectures (HSK, NV, MTK, MJI), pp. 275–283.

DAC-2002-BonaSSZSZ #clustering #embedded #energy #estimation #optimisation

Energy estimation and optimization of embedded VLIW processors based on instruction clustering (AB, MS, DS, VZ, CS, RZ), pp. 886–891.

DATE-2002-BonaSSZSZ #embedded #estimation #optimisation

An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores (AB, MS, DS, VZ, CS, RZ), p. 1128.

DATE-2002-RizzoC #architecture #case study #configuration management #video

A Video Compression Case Study on a Reconfigurable VLIW Architecture (DR, OC), pp. 540–546.

SAC-2002-JeeP #evaluation #performance

Performance evaluation for a compressed-VLIW processor (SJ, KP), pp. 913–917.

LCTES-SCOPES-2002-FengH #automation #verification

Automatic formal verification for scheduled VLIW code (XF, AJH), pp. 85–92.

LCTES-SCOPES-2002-KesslerB #architecture #clustering #code generation

Optimal integrated code generation for clustered VLIW architectures (CWK, AB), pp. 102–111.

LCTES-SCOPES-2002-QianCS #architecture #clustering

Loop fusion for clustered VLIW architectures (YQ, SC, PHS), pp. 112–119.

DAC-2001-JacomeVP #architecture #clustering

Clustered VLIW Architectures with Predicated Switching (MFJ, GdV, SP), pp. 696–701.

DAC-2001-LapinskiiJV #clustering

High-Quality Operation Binding for Clustered VLIW Datapaths (VSL, MFJ, GdV), pp. 702–707.

DAC-2001-VelevB #effectiveness #satisfiability #verification

Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors (MNV, REB), pp. 226–231.

DATE-2001-BekooijEWB #behaviour #functional

Functional units with conditional input/output behavior in VLIW processors (MB, LJME, AvdW, NGB), p. 822.

DATE-2001-SamiSSZZ #embedded

Exploiting data forwarding to reduce the power budget of VLIW embedded processors (MS, DS, CS, VZ, RZ), pp. 252–257.

DATE-2001-TerechkoPE #architecture #clustering #named

PRMDL: a machine description language for clustered VLIW architectures (AT, EJDP, JTJvE), p. 821.

CC-2001-Touati

Register Saturation in Superscalar and VLIW Codes (SAAT), pp. 213–228.

LCTES-OM-2001-GranstonSZ #architecture #pipes and filters

Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture (EDG, ES, JZ), pp. 138–144.

DAC-2000-GebotysGW #architecture #power management

Power minimization derived from architectural-usage of VLIW processors (CHG, RJG, SW), pp. 308–311.

DATE-2000-HaugKR #design #framework #hardware

A Hardware Platform for VLIW Based Emulation of Digital Designs (GH, UK, WR), p. 747.

CAV-2000-Velev #execution #verification

Formal Verification of VLIW Microprocessors with Speculative Execution (MNV), pp. 296–311.

DATE-1999-AlippiFPS #approach #configuration management #design

A DAG-Based Design Approach for Reconfigurable VLIW Processors (CA, WF, LP, MS), pp. 778–779.

DATE-1999-Leupers #code generation #embedded

Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors (RL), p. 105–?.

LCTES-1999-StotzerL #architecture #scheduling

Modulo Scheduling for the TMS320C6x VLIW DSP Architecture (ES, ELL), pp. 28–34.

CC-1998-StumpelTK #architecture #compilation

VLIW Compilation Techniques for Superscalar Architectures (ES, MT, UK), pp. 234–248.

HPCA-1997-WolfeFDF #design #video

Datapath Design for a VLIW Video Signal Processor (AW, JF, SD, ESTF), pp. 24–35.

PLDI-1994-EbciogluGKSZ #compilation

VLIW Compilation Techniques in a Superscalar Environment (KE, RDG, KCK, GMS, IZ), pp. 36–48.

CC-1994-SlowikPP #compilation

Compiling Nested Loops for Limited Connectivity VLIWs (AS, GP, PP), pp. 143–157.

ASPLOS-1992-MahlkeCHRS #scheduling

Sentinel Scheduling for VLIW and Superscalar Processors (SAM, WYC, WmWH, BRR, MSS), pp. 238–247.

ASPLOS-1991-WolfeS #architecture

A Variable Instruction Stream Extension to the VLIW Architecture (AW, JPS), pp. 2–14.

PPoPP-1991-BakewellQW #concurrent #source code

Mapping Concurrent Programs to VLIW Processors (HB, DJQ, PYW), pp. 21–27.

PLDI-1988-Lam #effectiveness #pipes and filters #scheduling

Software Pipelining: An Effective Scheduling Technique for VLIW Machines (MSL), pp. 318–328.

Best-of-PLDI-1988-Lam88a #effectiveness #pipes and filters #scheduling

Software pipelining: an effective scheduling technique for VLIW machines (with retrospective) (MSL), pp. 244–256.

ASPLOS-1987-ColwellNOPR #architecture #compilation #scheduling

A VLIW Architecture for a Trace Scheduling Compiler (RPC, RPN, JJO, DBP, PKR), pp. 180–192.