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Travelled to:
1 × USA
Collaborated with:
C.E.Leiserson
Talks about:
algorithm (1) routabl (1) planar (1) layout (1) vlsi (1) test (1) rout (1)

Person: F. Miller Maley

DBLP DBLP: Maley:F=_Miller

Contributed to:

STOC 19851985

Wrote 1 papers:

STOC-1985-LeisersonM #algorithm #testing
Algorithms for Routing and Testing Routability of Planar VLSI Layouts (CEL, FMM), pp. 69–78.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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