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Used together with:
driven (10)
placement (8)
rout (6)
awar (3)
packag (3)

Stem routabl$ (all stems)

22 papers:

DACDAC-2014-ChenHCCW #metaprogramming
Routability-Driven Blockage-Aware Macro Placement (YFC, CCH, CHC, YWC, CJW), p. 6.
DACDAC-2014-LinC #effectiveness
POLAR 2.0: An Effective Routability-Driven Placer (TL, CC), p. 6.
Metal layer planning for silicon interposers with consideration of routability and manufacturing cost (WHL, TKC, TCW), pp. 1–6.
DACDAC-2013-HeHCKLCY #integration #quality
Ripple 2.0: high quality routability-driven placement via global router integration (XH, TH, WKC, JK, KCL, WC, EFYY), p. 6.
DACDAC-2013-HsuCHCC #design
Routability-driven placement for hierarchical mixed-size circuit designs (MKH, YFC, CCH, TCC, YWC), p. 6.
DACDAC-2013-LiuKL #optimisation
Optimization of placement solutions for routability (WHL, CKK, YLL), p. 9.
DACDAC-2012-ViswanathanASLW #benchmark #contest #metric
The DAC 2012 routability-driven placement contest and benchmark suite (NV, CJA, CCNS, ZL, YW), pp. 774–782.
DACDAC-2012-WeiSVLARHTKS #evaluation #named
GLARE: global and local wiring aware routability evaluation (YW, CCNS, NV, ZL, CJA, LNR, ADH, GET, DK, SSS), pp. 768–773.
DACDAC-2012-ZhangC #named
GDRouter: interleaved global routing and detailed routing for ultimate routability (YZ, CC), pp. 597–602.
DATEDATE-2009-LuCLS #co-evolution #design
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design (CHL, HMC, CNJL, WYS), pp. 845–850.
DACDAC-2008-JiangSC #design #scalability
Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs (ZWJ, BYS, YWC), pp. 167–172.
Topological routing to maximize routability for package substrate (SL, GC, TTJ, LH, TZ, RD, XH), pp. 566–569.
DATEDATE-2007-SpindlerJ #estimation #performance
Fast and accurate routing demand estimation for efficient routability-driven placement (PS, FMJ), pp. 1226–1231.
DACDAC-2002-KannanBB #estimation #metric #on the
On metrics for comparing routability estimation methods for FPGAs (PK, SB, DB), pp. 70–75.
DACDAC-2000-CaldwellKM #question #recursion
Can recursive bisection alone produce routable placements? (AEC, ABK, ILM), pp. 477–482.
DACDAC-1995-LeeW #performance
A Performance and Routability Driven Router for FPGAs Considering Path Delays (YSL, ACHW), pp. 557–561.
DACDAC-1994-ZhuW #bound
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs (KZ, DFW), pp. 165–170.
DACDAC-1993-ChanSZ #array #on the #predict #programmable
On Routability Prediction for Field-Programmable Gate Arrays (PKC, MDFS, JYZ), pp. 326–330.
DACDAC-1993-VaishnavP #optimisation
Routability-Driven Fanout Optimization (HV, MP), pp. 230–235.
DACDAC-1991-DaiKS #sketching
Routability of a Rubber-Band Sketch (WWMD, RK, MS), pp. 45–48.
STOCSTOC-1985-LeisersonM #algorithm #testing
Algorithms for Routing and Testing Routability of Planar VLSI Layouts (CEL, FMM), pp. 69–78.
DACDAC-1973-So #multi
Pin assignment of circuit cards and the routability of multilayer printed wiring backplanes (HCS), pp. 33–43.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.