Stem vlsi$ (all stems)

290 papers:

DAC-2015-PanthSDL #3d #clustering #mobile #power management #trade-off

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications (SP, KS, YD, SKL), p. 6.

DAC-2015-VasudevanR #algorithm #performance

An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form (VV, MR), p. 6.

DATE-2015-HanyuSOMNM #architecture #in memory #paradigm #power management #reliability #towards

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm (TH, DS, NO, SM, MN, AM), pp. 1006–1011.

DATE-2013-KumarK #3d

Crosstalk avoidance codes for 3D VLSI (RK, SPK), pp. 1673–1678.

DATE-2013-ZhaiYZ #algorithm #float #random

GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects (KZ, WY, HZ), pp. 1661–1666.

DAC-2012-Gester0NPSV #algorithm #data type #performance

Algorithms and data structures for fast and good VLSI routing (MG, DM, TN, CP, CS, JV), pp. 459–464.

DATE-2012-Brenner

VLSI legalization with minimum perturbation by iterative augmentation (UB), pp. 1385–1390.

DATE-2011-Struzyna #clustering #constraints

Flow-based partitioning and position constraints in VLSI placement (MS), pp. 607–612.

DAC-2010-ChoRXP #network #using

History-based VLSI legalization using network flow (MC, HR, HX, RP), pp. 286–291.

DAC-2010-JindalAHLNW #detection #logic

Detecting tangled logic structures in VLSI netlists (TJ, CJA, JH, ZL, GJN, CBW), pp. 603–608.

DATE-2010-CupaiuoloST #architecture #detection #ml #throughput

Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector (TC, MS, AT), pp. 1396–1401.

ICPR-2010-KryszczukHS #orthogonal #predict #using

Direct Printability Prediction in VLSI Using Features from Orthogonal Transforms (KK, PH, RS), pp. 2764–2767.

DAC-2009-PatilLZWM #logic #using

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions (NP, AL, JZ, HSPW, SM), pp. 304–309.

DATE-2009-MitraZPW #logic #using

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors (SM, JZ, NP, HW), pp. 436–441.

DAC-2008-LiuTCC #correlation #modelling #statistics

Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications (JHL, MFT, LC, CCPC), pp. 694–697.

DATE-2008-SrivastavaSB #multi

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate (NS, RS, KB), pp. 426–431.

DATE-2008-ZezzaM #implementation

VLSI implementation of SISO arithmetic decoders for joint source channel coding (SZ, GM), pp. 1075–1078.

DAC-2007-Liu #correlation #design #framework #modelling

A General Framework for Spatial Correlation Modeling in VLSI Design (FL), pp. 817–822.

POPL-2007-Ghica #approach #design #geometry #synthesis

Geometry of synthesis: a structured approach to VLSI design (DRG), pp. 363–375.

DAC-2006-BanerjeeS #future of #question

Are carbon nanotubes the future of VLSI interconnections? (KB, NS), pp. 809–814.

DAC-2006-BurginCHMMSKFF #adaptation #algorithm #architecture #implementation #power management #trade-off

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm (FB, FC, MH, HM, RMP, RS, HK, NF, WF), pp. 558–561.

DATE-2006-DuttA #incremental #locality #performance #using

Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations (SD, HA), pp. 768–773.

DAC-2005-ZhaoZD #constraints #robust

Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits (CZ, YZ, SD), pp. 190–195.

DATE-2005-LiS #performance #simulation

An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation (ZL, CJRS), pp. 752–757.

DATE-2005-NoguchiN #monitoring #multi

On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits (KN, MN), pp. 146–151.

DATE-2005-TiriV05a #design

A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs (KT, IV), pp. 58–63.

DATE-2003-VerderberZL #implementation #optimisation #video

HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder (MV, AZ, DL), pp. 20238–20243.

HPCA-2003-KhailanyDRKOT #scalability

Exploring the VLSI Scalability of Stream Processors (BK, WJD, SR, UJK, JDO, BT), pp. 153–164.

DATE-2002-AbabeiB #clustering #statistics

Statistical Timing Driven Partitioning for VLSI Circuits (CA, KB), p. 1109.

DATE-2002-BystrovKY #design #modelling #partial order #visualisation

Visualization of Partial Order Models in VLSI Design Flow (AVB, MK, AY), p. 1089.

DATE-2002-CarmonaJDER #design #programmable

Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip (RCG, FJG, RDC, SEM, ÁRV), pp. 362–366.

DATE-2002-YmeriNMRSV #approach #parametricity #performance

Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate (HY, BN, KM, DDR, MS, SV), p. 1113.

POPL-2002-Manohar #design #scalability

Scalable formal design methods for asynchronous VLSI (RM), pp. 245–246.

DAC-2001-BaiBH #analysis #power management

Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits (GB, SB, INH), pp. 295–300.

DAC-2001-Restle #design #visualisation

Technical Visualizations in VLSI Design (PR), pp. 494–499.

DAC-2001-SolomonH #layout #using

Using Texture Mapping with Mipmapping to Render a VLSI Layout (JS, MH), pp. 500–505.

DAC-2000-KirovskiLWP #forensics #tool support

Forensic engineering techniques for VLSI CAD tools (DK, DTL, JLW, MP), pp. 581–586.

DATE-2000-FrohlichGF #clustering #parallel #simulation

A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level (NF, VG, JF), pp. 679–684.

KDD-2000-FountainDS #mining #testing

Mining IC test data to optimize VLSI testing (TF, TGD, BS), pp. 18–25.

DAC-1999-BanerjeeMSH #on the

On Thermal Effects in Deep Sub-Micron VLSI Interconnects (KB, AM, ALSV, CH), pp. 885–891.

DAC-1999-CaldwellKKM #clustering #development #heuristic

Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting (AEC, ABK, AAK, ILM), pp. 349–354.

DAC-1999-ChuangP #design #perspective

SOI Digital CMOS VLSI — a Design Perspective (CTC, RP), pp. 709–714.

DAC-1999-IsmailF

Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits (YII, EGF), pp. 721–724.

DAC-1999-KhatriMBOS #layout #novel

A Novel VLSI Layout Fabric for Deep Sub-Micron Applications (SPK, AM, RKB, RHJMO, ALSV), pp. 491–496.

DAC-1999-SundararajanP #power management #synthesis #using

Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages (VS, KKP), pp. 72–75.

DAC-1999-TanSLLY #linear #network #optimisation #sequence

Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings (XDT, CJRS, DL, JCL, LPY), pp. 78–83.

DATE-1999-Hsiao #estimation #optimisation #scalability #search-based #using

Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits (MSH), p. 175–?.

DATE-1999-MaamarR #adaptation #named #testing

ADOLT — An ADaptable On — Line Testing Scheme for VLSI Circuits (AM, GR), pp. 770–771.

DATE-1999-NiggemeyerR #parametricity #self

Parametric Built-In Self-Test of VLSI Systems (DN, MR), p. 376–?.

DAC-1998-CuletuAM

A Practical Repeater Insertion Method in High Speed VLSI Circuits (JC, CA, JM), pp. 392–395.

DAC-1998-NemaniN #estimation #perspective

Delay Estimation VLSI Circuits from a High-Level View (MN, FNN), pp. 591–594.

DAC-1998-OhH #data flow #design #graph

Rate Optimal VLSI Design from Data Flow Graph (MO, SH), pp. 118–121.

DAC-1998-OrshanskyCH #performance #simulation #statistics

A Statistical Performance Simulation Methodology for VLSI Circuits (MO, JCC, CH), pp. 402–407.

DATE-1998-Montiel-NelsonASN #compilation #design

A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design (JAMN, VdA, RS, AN), pp. 947–948.

DATE-1998-UrrizaAGBN #architecture #image #using

VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform (IU, JIA, JIGN, LAB, DN), pp. 196–201.

DAC-1997-ChenL #analysis #design #power management

Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design (HHC, DDL), pp. 638–643.

DAC-1997-DengiR #2d #modelling

Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling (EAD, RAR), pp. 127–132.

DAC-1997-DingWHP #cumulative #estimation #statistics

Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Cirucits (CSD, QW, CTH, MP), pp. 371–376.

DAC-1997-KarypisAKS #clustering #multi

Multilevel Hypergraph Partitioning: Application in VLSI Domain (GK, RA, VK, SS), pp. 526–529.

EDTC-1997-Fishburn

Shaping a VLSI wire to minimize Elmore delay (JPF), pp. 244–251.

EDTC-1997-SzekelyPPRC #simulation

SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells (VS, AP, AP, MR, AC), p. 617.

SAC-1997-MoonLK #2d #clustering #search-based

Genetic VLSI circuit partitioning with two-dimensional geographic crossover and zigzag mapping (BRM, YSL, CKK), pp. 274–278.

DAC-1996-ChengTDRK #named #reliability

iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips (YKC, CCT, AD, ER, SMK), pp. 548–551.

DAC-1996-DuttD #approach #clustering

A Probability-Based Approach to VLSI Circuit Partitioning (SD, WD), pp. 100–105.

DAC-1996-FujimotoK #design #verification

VLSI Design and System Level Verification for the Mini-Disc (TF, TK), pp. 491–496.

DAC-1996-Johannes #clustering

Partitioning of VLSI Circuits and Systems (FMJ), pp. 83–87.

DAC-1996-TengCRK #reliability

Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects (CCT, YKC, ER, SMK), pp. 752–757.

DAC-1996-TodescoM #named #parallel #simulation

Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems (ARWT, THYM), pp. 149–154.

STOC-1996-AggarwalKW #layout #trade-off

Node-Disjoint Paths on the Mesh and a New Trade-Off in VLSI Layout (AA, JMK, DPW), pp. 585–594.

ICPR-1996-AruruRN #architecture #image

A VLSI system architecture for lossless image compression (SBA, NR, KRN), pp. 594–598.

ICPR-1996-FerrariBG #array #classification

A VLSI array processor accelerator for k-NN classification (AF, MB, RG), pp. 723–727.

SAC-1996-GabrielliGM #design #fuzzy #process

VLSI design of a fuzzy chip that processes 2-4 inputs every 160-320 ns whichever is the fuzzy system (AG, EG, MM), pp. 590–594.

DAC-1995-Chamberlain #logic #parallel #simulation

Parallel Logic Simulation of VLSI Systems (RDC), pp. 139–143.

DAC-1995-DevadasM #bibliography #optimisation #power management

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits (SD, SM), pp. 242–247.

DAC-1995-HagenHK #heuristic #layout #quantifier

Quantified Suboptimality of VLSI Layout Heuristics (LWH, DJHH, ABK), pp. 216–221.

DAC-1995-Najm #correlation #estimation #feedback

Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits (FNN), pp. 612–617.

DAC-1995-NajmZ #process #worst-case

Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits (FNN, MYZ), pp. 623–627.

FPCA-1995-SharpR #specification #using

Using a Language of Functions and Relations for VLSI Specification (RS, OR), pp. 45–54.

SAC-1995-GandolfiGMR #configuration management #design #fuzzy

Design of a VLSI very high speed reconfigurable digital fuzzy processor (EG, AG, MM, MR), pp. 477–481.

HPCA-1995-SastryR #architecture #distance

A VLSI Architecture for Computer the Tree-to-Tree Distance (RS, NR), pp. 330–339.

DAC-1994-HarrisO #architecture #concurrent #design #synthesis

Microarchitectural Synthesis of VLSI Designs with High Test Concurrency (IGH, AO), pp. 206–211.

DAC-1994-KahngM #analysis #equation #using

Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model (ABK, SM), pp. 563–569.

DAC-1994-Maly #design #perspective

Cost of Silicon Viewed from VLSI Design Perspective (WM), pp. 135–142.

DAC-1994-MehrotraFL #approach #optimisation #probability

Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits (SM, PDF, WL), pp. 36–40.

EDAC-1994-VacherBGRS #fourier #implementation #parallel #performance

A VLSI Implementation of Parallel Fast Fourier Transform (AV, MB, AG, TR, AS), pp. 250–255.

EDAC-1994-WangFF

An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits (JHW, JTF, WSF), pp. 562–566.

DAC-1993-CarlsonC #order #performance

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering (BSC, CYRC), pp. 361–366.

DAC-1993-CongS #algorithm #bottom-up #clustering #design #parallel

A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design (JC, MS), pp. 755–760.

DAC-1993-DaoMHOM

A Compaction Method for Full Chip VLSI Layouts (JD, NM, TH, CO, SM), pp. 407–412.

DAC-1993-DharchoudhuryK #variability #worst-case

Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits (AD, SMK), pp. 154–158.

DAC-1993-SilvaK #design #documentation #interface

Active Documentation: A New Interface for VLSI Design (MJS, RHK), pp. 654–660.

DAC-1993-Yarnikh

The State of CAD and VLSI in Russia (VY), pp. 707–708.

ICDAR-1993-TangLL #algorithm #implementation #pattern matching #pattern recognition #recognition

VLSI implementation for HVRI algorithm in pattern recognition (YYT, TL, SWL), pp. 460–463.

SIGMOD-1993-SinghalAL #design #named #object-oriented

DDB: An Object Oriented Design Data Manager for VLSI CAD (AS, RMA, CYL), pp. 467–470.

HCI-ACS-1993-GamoSKMH #automation #collaboration

Collaboration of Line and Staff in Fully Automated VLSI Factory (YG, WS, KK, HM, TH), pp. 540–545.

SEKE-1993-BombanaBCFSZ #analysis #functional #testing

An Expert Solution to Functional Testability Analysis of VLSI Circuits (MB, GB, PC, FF, DS, GZ), pp. 263–265.

SEKE-1993-BourbakisR #automation #reverse engineering #visual notation

An Expert Tool For Automatic Visual VLSI Reverse Engineering (NGB, DR), pp. 73–77.

DAC-1992-Gebotys #embedded #scheduling

Optimal Scheduling and Allocation of Embedded VLSI Chips (CHG), pp. 116–119.

DAC-1992-Sur-KolayB #canonical

Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning (SSK, BBB), pp. 69–74.

DAC-1991-Chen #clustering #concurrent #graph #scheduling

Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit (CIHC), pp. 287–290.

DAC-1991-FangCFC #multi #problem

Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems (SCF, KEC, WSF, SJC), pp. 60–65.

DAC-1991-Harrison #layout #using

VLSI Layout Compaction Using Radix Priority Search Trees (AJH), pp. 732–735.

DAC-1991-Hwang #analysis #named

REX — A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis (JPH), pp. 717–722.

DAC-1991-MassonEBWC #implementation #lisp #object-oriented

Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing System (CM, RE, DB, DW, GC), pp. 259–264.

DAC-1991-WuR #effectiveness #evaluation

Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits (DMW, CER), pp. 291–295.

SIGMOD-1991-ChiuehK #design #named

Trait: An Attribute Management System for VLSI Design Objects (TcC, RHK), pp. 228–237.

ML-1991-Herrmann #learning

Learning Analytical Knowledge About VLSI-Design from Observation (JH), pp. 610–614.

DAC-1990-CarlsonR #algorithm #design #evaluation #parallel #performance #verification

Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW (ECC, RAR), pp. 253–259.

DAC-1990-Jabri #knowledge-based #named #prolog

BREL — a Prolog Knowledge-based System Shell for VLSI CAD (MAJ), pp. 272–277.

DAC-1990-Spreitzer #design

Comparing Structurally Different Views of a VLSI Design (MS), pp. 200–212.

DAC-1990-SutanthavibulS #adaptation #layout

An Adaptive Timing-Driven Layout for High Speed VLSI (SS, ES), pp. 90–95.

DAC-1989-BolsensRCM #analysis #behaviour #debugging #logic

Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (IB, WDR, LJMC, HDM), pp. 513–518.

DAC-1989-BonapaceL #algorithm #design

An O(nlogm) Algorithm for VLSI Design Rule Checking (CRB, CYL), pp. 503–507.

DAC-1989-DuttaM #automation #network

Automatic Sizing of Power/Ground (P/G) Networks in VLSI (RD, MMS), pp. 783–786.

DAC-1989-Ghewala #named #testing

CrossCheck: A Cell Based VLSI Testability Solution (TG), pp. 706–709.

DAC-1989-HoevenLDD #network #simulation

A New Model for the High Level Description and Simulation of VLSI Networks (AJvdH, AAdL, EFD, PD), pp. 738–741.

DAC-1989-JonePP #concurrent #testing

A Scheme for Overlaying Concurrent Testing of VLSI Circuits (WBJ, CAP, MP), pp. 531–536.

DAC-1989-Karatsu #design #standard

VLSI Design Language Standardization Effort in Japan (OK), pp. 50–55.

DAC-1989-SiepmannZ #design #object-oriented

An Object-Oriented Datamodel for the VLSI Design System PLAYOUT (ES, GZ), pp. 814–817.

DAC-1989-WaterkampWBRS #layout

Technology Tracking of Non Manhattan VLSI Layout (JW, RW, RB, MR, GS), pp. 296–301.

DAC-1989-WeninVCLG #layout #rule-based #verification

Rule-based VLSI Verification System Constrained by Layout Parasitics (JW, JV, MVC, JL, PG), pp. 662–667.

DAC-1989-Yu #case study

A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD (MLY), pp. 412–417.

FPCA-1989-WeissSS #architecture #array #data-driven

Architectural Improvements for Data-Driven VLSI Processing Arrays (SW, IYS, GMS), pp. 243–259.

DAC-1988-BaerLMNSW #multi

A Notation for Describing Multiple Views of VLSI Circuits (JLB, MCL, LM, RN, LS, WW), pp. 102–107.

DAC-1988-BarthS #design #representation

A Structural Representation for VLSI Design (RB, BS), pp. 237–242.

DAC-1988-BergstraesserGHW #architecture #named #synthesis #tool support

SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture (TB, JG, KH, SW), pp. 654–657.

DAC-1988-Cai #multi

Multi-Pads, Single Layer Power Net Routing in VLSI Circuits (HC), pp. 183–188.

DAC-1988-ChenB #layout

A Module Area Estimator for VLSI Layout (XC, MLB), pp. 54–59.

DAC-1988-ChenP #database #design

A Database Management System for a VLSI Design System (GDC, TMP), pp. 257–262.

DAC-1988-ChiangNL #algorithm #analysis #performance

Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2 (KWC, SN, CYL), pp. 471–475.

DAC-1988-GebotysE #design #synthesis #testing

VLSI Design Synthesis with Testability (CHG, MIE), pp. 16–21.

DAC-1988-HenkelG #layout #named #set #verification

RISCE — A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification (VH, UG), pp. 465–470.

DAC-1988-KuoF #configuration management #scalability

Spare Allocation and Reconfiguration in Large Area VLSI (SYK, WKF), pp. 609–612.

DAC-1988-WidyaLW #concurrent #database #design

Concurrency Control in a VLSI Design Database (IW, TGRvL, PvdW), pp. 357–362.

DAC-1988-WimerKC

Optimal Aspect Ratios of Building Blocks in VLSI (SW, IK, IC), pp. 66–72.

DAC-1988-WolfL #data transformation #modelling

Object Type Oriented Data Modeling for VLSI Data Management (PvdW, TGRvL), pp. 351–356.

DAC-1988-XiongK #design #problem

The Constrained Via Minimization Problem for PCB and VLSI Design (XMX, ESK), pp. 573–578.

DAC-1988-Zimmerman #estimation

A New Area and Shape Function Estimation Technique for VLSI Layouts (GZ), pp. 60–65.

STOC-1988-AggarwalCR #energy

Energy Consumption in VLSI Circuits (Preliminary Version) (AA, AKC, PR), pp. 205–216.

JICSCP-1988-Reintjes88 #design #prolog

A VLSI Design Environment in PROLOG (PBR), pp. 70–81.

DAC-1987-CarpenterH #constraints #generative #incremental

Generating Incremental VLSI Compaction Spacing Constraints (CWC, MH), pp. 291–297.

DAC-1987-DemersJFC #integration #named #object-oriented #tool support

CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools (LPD, PJ, SF, EC), pp. 750–756.

DAC-1987-LathropHK #abstraction #functional #modelling #simulation

Functional Abstraction from Structure in VLSI Simulation Models (RHL, RJH, RSK), pp. 822–828.

DAC-1987-Maly #fault #modelling #testing

Realistic Fault Modeling for VLSI Testing (WM), pp. 173–180.

DAC-1987-Steele #design

An Expert System Application in Semicustom VLSI Design (RLS), pp. 679–688.

DAC-1987-WongL #array #optimisation #synthesis

Array Optimization for VLSI Synthesis (DFW, CLL), pp. 537–543.

DAC-1987-YuKL #adaptation #optimisation #testing #using

VLSI Circuit Testing Using an Adaptive Optimization Model (PSY, CMK, YHL), pp. 399–406.

SIGIR-1987-MukherjeeB #performance #retrieval

A VLSI Chip for Efficient Transmission and Retrieval of Information (AM, MAB), pp. 208–216.

ASPLOS-1987-BeckKT #multi

VLSI Assist For a Multiprocessor (BB, BK, SST), pp. 10–20.

DAC-1986-AdolphRS #design #representation

A frame based system for representing knowledge about VLSI design: a proposal (WSA, HKR, AS), pp. 671–676.

DAC-1986-BushnellD #integration #tool support #using

VLSI CAD tool integration using the Ulysses environment (MLB, SWD), pp. 55–61.

DAC-1986-DevadasN #array #named #synthesis

GENIE: a generalized array optimizer for VLSI synthesis (SD, ARN), pp. 631–637.

DAC-1986-FrisonG #editing #layout #metaprogramming #named

MADMACS: a new VLSI layout macro editor (PF, EG), pp. 654–658.

DAC-1986-Hartoog #analysis #layout #standard

Analysis of placement procedures for VLSI standard cell layout (MRH), pp. 314–319.

DAC-1986-KurdahiP #estimation #named

PLEST: a program for area estimation of VLSI integrated circuits (FJK, ACP), pp. 467–473.

DAC-1986-Larsen #analysis #clustering #data type #synthesis

Rules-based object clustering: a data structure for symbolic VLSI synthesis and analysis (RPL), pp. 768–777.

DAC-1986-LathropK

Precedent-based manipulation of VLSI structures (RHL, RSK), pp. 667–670.

DAC-1986-Maly #order #sequence #testing

Optimal order of the VLSI IC testing sequence (WM), pp. 560–566.

DAC-1986-NandyR #design #representation

Dual quadtree representation for VLSI designs (SKN, LVR), pp. 663–666.

DAC-1986-Peng #design #synthesis

Synthesis of VLSI systems with the CAMAD design aid (ZP), pp. 278–284.

DAC-1986-WatanabeA #design #named

Flute — a floorplanning agent for full custom VLSI design (HW, BDA), pp. 601–607.

DAC-1986-Wolf #database #object-oriented

An object-oriented, procedural database for VLSI chip planning (WW), pp. 744–751.

STOC-1986-Siegel #aspect-oriented #data flow

Aspects of Information Flow in VLSI Circuits (Extended Abstract) (AS), pp. 448–459.

POPL-1986-Chen #compilation #parallel

A Parallel Language and its Compilation to Multiprocessor Machines or VLSI (MCC), pp. 131–139.

POPL-1986-JonesS #attribute grammar #design

Hierarchical VLSI Design Systems Based on Attribute Grammars (LGJ, JS), pp. 58–69.

ICLP-1986-Gupta86 #generative #prolog

Test-pattern Generation for VLSI Circuits in a Prolog Environment (RG), pp. 528–535.

DAC-1985-AndouYMKSH #algorithm #automation

Automatic routing algorithm for VLSI (HA, IY, YM, YK, KS, KH), pp. 785–788.

DAC-1985-AnwayFR #layout

PLINT layout system for VLSI chips (HA, GF, RR), pp. 449–452.

DAC-1985-ChowdhuryB

The construction of minimal area power and ground nets for VLSI circuits (SUC, MAB), pp. 794–797.

DAC-1985-ChuL #design #layout #tool support

Technology tracking for VLSI layout design tools (KCC, YEL), pp. 279–285.

DAC-1985-Cory #layout #named

Layla: a VLSI layout language (WEC), pp. 245–251.

DAC-1985-EliasBCM #design #integration #multi

The ITT VLSI design system: CAD integration in a multi-national environment (NJE, RJB, ADC, RMM), pp. 549–553.

DAC-1985-Frank #data-driven #simulation #using

Switch-level simulation of VLSI using a special-purpose data-driven computer (EHF), pp. 735–738.

DAC-1985-GuptaA #fault #functional #modelling #simulation

Functional fault modeling and simulation for VLSI devices (AKG, JRA), pp. 720–726.

DAC-1985-HutchingsBF

Integrated VLSI CAD systems at Digital Equipment Corporation (AFH, RJB, WMF), pp. 543–548.

DAC-1985-KosekiY #design #named

PLAYER: a PLA design system for VLSI’s (YK, TY), pp. 766–769.

DAC-1985-KowalskiT #automation #design #knowledge base #what

The VLSI design automation assistant: what’s in a knowledge base (TJK, DET), pp. 252–258.

DAC-1985-Mata #named #specification

ALLENDE: a procedural language for the hierarchical specification of VLSI layouts (JMdM), pp. 183–189.

DAC-1985-Matson #megamodelling

Macromodeling of digital MOS VLSI Circuits (MDM), pp. 141–151.

DAC-1985-McLellan #data transformation #design #effectiveness

Effective data management for VLSI design (PM), pp. 652–657.

DAC-1985-MuraokaIKMH #analysis #named

ACTAS: an accurate timing analysis system for VLSI (MM, HI, HK, MM, KH), pp. 152–158.

DAC-1985-RamayyaKP #automation #canonical

An automated data path synthesizer for a canonic structure, implementable in VLSI (KR, AK, SP), pp. 381–387.

DAC-1985-Tendolkar #analysis #fault #random

Analysis of timing failures due to random AC defects in VLSI modules (NNT), pp. 709–714.

DAC-1985-WinslettBPW #database #design #relational

Relational and entity-relationship model databases and specialized design files in VLSI design (MW, RB, THP, GW), pp. 410–416.

SIGMOD-1985-BatoryK #concept #modelling

Modeling Concepts for VLSI CAD Objects (Abstract) (DSB, WK), p. 446.

VLDB-1985-AfsarmaneshMKP #approach #database #object-oriented

An Extensible Object-Oriented Approach to Databases for VLSI/CAD (HA, DM, DK, ACP), pp. 13–24.

STOC-1985-Aggarwal #modelling #trade-off

Tradeoffs for VLSI Models with Subpolynomial Delay (AA), pp. 59–68.

STOC-1985-LeisersonM #algorithm #testing

Algorithms for Routing and Testing Routability of Planar VLSI Layouts (CEL, FMM), pp. 69–78.

POPL-1985-AnantharamanCFM #compilation

Compiling Path Expressions into VLSI Circuits (TSA, EMC, MJF, BM), pp. 191–204.

DAC-1984-AshokMR #design #problem #process

Uniform support for information handling and problem solving required by the VLSI design process (VA, WLM, JR), pp. 694–696.

DAC-1984-DasguptaGRWW #clustering #design #testing

Chip partitioning aid: A design technique for partitionability and testability in VLSI (SD, MCG, RAR, RGW, TWW), pp. 203–208.

DAC-1984-Gajski #compilation

Silicon compilers and expert systems for VLSI (DDG), pp. 86–87.

DAC-1984-GlasserH #optimisation

Delay and power optimization in VLSI circuits (LAG, LH), pp. 529–535.

DAC-1984-KozawaMT #algorithm #layout #logic #top-down

Combine and top down block placement algorithm for hierarchical logic VLSI layout (TK, CM, HT), pp. 667–669.

DAC-1984-KozminskiK #algorithm #graph

An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuits (KK, EK), pp. 655–656.

DAC-1984-KrieteN #design #metaprogramming #parametricity

A VLSI design methodology based on parametric macro cells (RAK, RKN), pp. 686–688.

DAC-1984-LotvinJG #layout #named

Amoeba: A symbolic VLSI layout system (ML, BJ, RG), pp. 294–300.

DAC-1984-MeyerAP #automaton #design

A VLSI FSM design system (MJM, PA, RGP), pp. 434–440.

DAC-1984-Mori #interactive #layout

Interactive compaction router for VLSI layout (HM), pp. 137–143.

DAC-1984-Ousterhout #modelling

Switch-level delay models for digital MOS VLSI (JKO), pp. 542–548.

DAC-1984-OusterhoutHMST #layout #named

Magic: A VLSI layout system (JKO, GTH, RNM, WSS, GST), pp. 152–159.

DAC-1984-OzakiWKIS #layout #named

MGX: An integrated symbolic layout system for VLSI (MO, MW, MK, MI, KS), pp. 572–579.

DAC-1984-SaucierB #control flow #using

VLSI test expertise system using a control flow model (GS, CB), pp. 497–503.

DAC-1984-SteinbergM #approach #knowledge base

A knowledge based approach to VLSI CAD the redesign system (LIS, TMM), pp. 412–418.

DAC-1984-SuL #functional #testing

Functional testing techniques for digital LSI/VLSI systems (SYHS, TL), pp. 517–528.

VLDB-1984-AdibaN #data transformation #information management

Information Processing for CAD/VLSI on a Generalized Data Management System (MEA, GTN), pp. 371–374.

VLDB-1984-Tanaka #algorithm

Bit-Sliced VLSI Algorithm for Search and Sort (YT), pp. 225–234.

STOC-1984-BilardiP #network #sorting

A Minimum Area VLSI Network for O(log n) Time Sorting (GB, FPP), pp. 64–70.

STOC-1984-Blum #layout #trade-off

An Area-Maximum Edge Length Tradeoff for VLSI Layout (NB), pp. 92–97.

STOC-1984-Mirzaian

Channel Routing in VLSI (Extended Abstract) (AM), pp. 101–107.

ICALP-1984-MehlhornP #integer #multi

Area-Time Optimal VLSI Integer Multiplier with Minimum Computation Time (KM, FPP), pp. 347–357.

ICALP-1984-Rosenberg

The VLSI Revolution in Theoretical Circles (ALR), pp. 23–40.

LFP-1984-Sheeran #design

muFP, A Language for VLSI Design (MS), pp. 104–112.

DAC-1983-AhdootAC #design

IBM FSD VLSI chip design methodology (KA, RRA, LC), pp. 39–45.

DAC-1983-ChangA #consistency

Consistency checking for MOS/VLSI circuits (NSC, RA), pp. 732–733.

DAC-1983-Druian #design #functional #modelling

Functional models for VLSI design (RLD), pp. 506–514.

DAC-1983-EliasW #compilation #design

The IC Module Compiler, a VLSI system design aid (NJE, AWW), pp. 46–49.

DAC-1983-Jouppi #analysis

Timing analysis for nMOS VLSI (NPJ), pp. 411–418.

DAC-1983-KowalskiT #automation #design #prototype #type system

The VLSI Design Automation Assistant: Prototype system (TJK, DET), pp. 479–483.

DAC-1983-LiaoW #algorithm #constraints #layout

An algorithm to compact a VLSI symbolic layout with mixed constraints (YZL, CKW), pp. 107–112.

DAC-1983-LieberherrK #hardware #named

Zeus: A hardware description language for VLSI (KJL, SEK), pp. 17–23.

DAC-1983-MayoO #layout

Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool (RNM, JKO), pp. 270–276.

DAC-1983-Moulton

Laying the power and ground wires on a VLSI chip (ASM), pp. 754–755.

DAC-1983-RosenbergBDDPPRW #design

A vertically integrated VLSI design environment (JBR, DGB, JAD, SWD, CJP, JP, CDR, NW), pp. 31–38.

DAC-1983-RothermelM #design #using

Routing method for VLSI design using irregular cells (HJR, DAM), pp. 257–262.

DAC-1983-SupowitS #algorithm

Placement algorithms for custom VLSI (KJS, EAS), pp. 164–170.

DAC-1983-SzymanskiW #algorithm #analysis #performance

Space efficient algorithms for VLSI artwork analysis (TGS, CJVW), pp. 734–739.

DAC-1983-TsukizoeSKF

MACH : a high-hitting pattern checker for VLSI mask data (AT, JS, TK, HF), pp. 726–731.

STOC-1983-AhoUY #on the

On Notions of Information Transfer in VLSI Circuits (AVA, JDU, MY), pp. 133–139.

ICALP-1983-HambruschS #bound #graph #problem

Lower Bounds for Solving Undirected Graph Problems on VLSI (SEH, JS), pp. 292–303.

ICALP-1983-LangSSS #algorithm #performance #sorting

A Fast Sorting Algorithm for VLSI (HWL, MS, HS, HS), pp. 408–419.

DAC-1982-AdachiKNS #design #layout #top-down

Hierarchical top-down layout design method for VLSI chip (TA, HK, MN, TS), pp. 785–791.

DAC-1982-Adshead #algorithm #complexity #hardware #problem #question #scalability #towards

Towards VLSI complexity: The DA algorithm scaling problem: can special DA hardware help? (HGA), pp. 339–344.

DAC-1982-BassetS #design #testing #top-down

Top down design and testability of VLSI circuits (PB, GS), pp. 851–857.

DAC-1982-DonzeSJS #design

Philo-a VLSI design system (RLD, JS, MJ, GS), pp. 163–169.

DAC-1982-EustaceM #approach #automaton #design #finite

A Deterministic finite automaton approach to design rule checking for VLSI (RAE, AM), pp. 712–717.

DAC-1982-Hassett #approach #automation #layout #problem

Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI (JEH), pp. 777–784.

DAC-1982-Hayes #fault #simulation

A fault simulation methodology for VLSI (JPH), pp. 393–399.

DAC-1982-Katz #approach #database #design

A database approach for managing VLSI design data (RHK), pp. 274–282.

DAC-1982-LiptonNSVV #named

ALI: A procedural language to describe VLSI layouts (RJL, SCN, RS, JV, GV), pp. 467–474.

DAC-1982-MinS #fault #functional #testing

Testing functional faults in VLSI (YM, SYHS), pp. 384–392.

DAC-1982-MudgeRLA #image #layout #validation

Cellular image processing techniques for VLSI circuit layout validation and routing (TNM, RAR, RML, DEA), pp. 537–543.

DAC-1982-OusterhoutU #design #metric

Measurements of a VLSI design (JKO, DMU), pp. 903–908.

DAC-1982-Putatunda #automation #named

Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips (RP), pp. 616–621.

DAC-1982-SmithW #data transformation #design #low cost

A low cost, transportable, data management system for LSI/VLSI design (DCS, BSW), pp. 283–290.

DAC-1982-TeelW #design #logic

A logic minimizer for VLSI PLA design (BT, DW), pp. 156–162.

DAC-1982-WipflerWM #algorithm #layout

A combined force and cut algorithm for hierarchical VLSI layout (GJW, MW, DAM), pp. 671–677.

STOC-1982-Carter #formal method #testing

The Theory of Signature Testing for VLSI (JLC), pp. 66–76.

STOC-1982-Kissin #energy

Measuring Energy Consumption in VLSI Circuits: a Foundation (GK), pp. 99–104.

STOC-1982-Leighton #layout

A Layout Strategy for VLSI which Is Provably Good (Extended Abstract) (FTL), pp. 85–98.

STOC-1982-MehlhornS #distributed

Las Vegas Is better than Determinism in VLSI and Distributed Computing (Extended Abstract) (KM, EMS), pp. 330–337.

POPL-1982-LiptonSV #aspect-oriented #programming

Programming Aspects of VLSI (RJL, RS, JV), pp. 57–65.

DAC-1981-Burdick #design #formal method #process #what

What to do when the seat of your pants wears out — the formalization of the VLSI design process (EB), pp. 708–709.

DAC-1981-ChibaOKNIK #layout #named

SHARPS: A hierarchical layout system for VLSI (TC, NO, TK, IN, TI, SK), pp. 820–827.

DAC-1981-Corbin

Custom VLSI electrical rule checking in an intelligent terminal (LVC), pp. 696–701.

DAC-1981-EdmondsonJ #layout #low cost #verification

A low cost hierarchical system for VLSI layout and verification (THE, RMJ), pp. 505–510.

DAC-1981-El-Ziq #automation #fault #generative #testing

Automatic test generation for stuck-open faults in CMOS VLSI (YMEZ), pp. 347–354.

DAC-1981-GoelR #automation #generative #logic #named #testing

PODEM-X: An automatic test generation system for VLSI logic structures (PG, BCR), pp. 260–268.

DAC-1981-Heller #design #physics

Contrasts in physical design between LSI and VLSI (WRH), pp. 676–683.

DAC-1981-KozawaTSMI #algorithm #concurrent

A concurrent pattern operation algorithm for VLSI mask data (TK, AT, JS, CM, TI), pp. 563–570.

DAC-1981-NgGK #parametricity #verification

A timing verification system based on extracted MOS/VLSI circuit parameters (PN, WG, RK), pp. 288–292.

DAC-1981-PatelC #clustering #problem

Partitioning for VLSI placement problems (AMP, LCC), pp. 411–418.

DAC-1981-PerskyES #automation #layout

The Hughes Automated Layout System — automated LSI/VLSI layout based on channel routing (GP, CE, DMS), pp. 22–28.

DAC-1981-Reitmeyer

CAD for military systems, an essential link to LSI, VLSI and VHSIC technology (RRJ), pp. 3–12.

DAC-1981-RothermelM #layout #power management

Computation of power supply nets in VLSI layout (HJR, DAM), pp. 37–42.

DAC-1981-Williams #automation #layout #verification

Automatic VLSI layout verification (LW), pp. 726–732.

VLDB-1981-MenonH #analysis #design #relational

Design and Analysis of a Relational Join Operation for VLSI (JM, DKH), pp. 44–55.

STOC-1981-ChazelleM #complexity

A Model of Computation for VLSI with Related Complexity Results (BC, LM), pp. 318–325.

STOC-1981-LiptonS #bound

Lower Bounds for VLSI (RJL, RS), pp. 300–307.

STOC-1981-Yao81a

The Entropic Limitations on VLSI Computations (Extended Abstract) (ACCY), pp. 308–311.

ICALP-1981-PreparataV #fourier #integer #multi #network

Area-Time Optimal VLSI Networks for Computing Integer Multiplications and Discrete Fourier Transform (FPP, JV), pp. 29–40.

DAC-1980-Allen #automation #design

A contemporary perspective on design automation and VLSI in the 80’s (Position Statement) (JA), pp. 338–339.

DAC-1980-Daram

Position statement — CAD for VLSI (SBD), p. 642.

DAC-1980-Gwyn #automation #design #roadmap

Design automation trends for VLSI in the 1980s (Position Statement) (CWG), p. 340.

DAC-1980-Jacobs #automation #design

Design automation and VLSI in the 80’s (Position Statement) (RMJ), p. 341.

DAC-1980-Lee #design #tool support

Design tools for VLSI (Position Statement) (BL), p. 342.

DAC-1980-Newton #challenge #design

The VLSI design challenge of the 80’s (Position Statement) (ARN), pp. 343–344.

DAC-1980-Roberts #challenge #design #named

VLSI — a challenge for system designers (Position Statement) (MBR), p. 345.

DAC-1980-Rosenberg #automation #design #evolution

The evolution of design automation to meet the challanges of VLSI (LMR), pp. 3–11.

DAC-1980-Sapiro #automation

Desisn automation and VLSI in the 80’s (Position Statement) (SS), pp. 346–347.

SIGMOD-1980-KungL #array #database #relational

Systolic (VLSI) Arrays for Relational Database Operations (HTK, PLL), pp. 105–116.

DAC-1979-Giuliani #design #tool support

Will Disign tools catch up to VLSI design (DG), pp. 544–545.

DAC-1979-Hightower #design #problem

Can CAD meet the VLSI design problems of the 80’s (DWH), pp. 552–553.

DAC-1979-Larsen #design #problem #question

Can CAD meet the VLSI design problems of the 80’s? (RPL), p. 551.

DAC-1979-Lattin #design #problem

VLSI design methodology the problem of the 80’s for microprocessor design (BL), pp. 548–549.

DAC-1979-LoslebenT #analysis

Topological analysis for VLSI circuits (PL, KT), pp. 461–473.

DAC-1979-Oakes #design

The complete VLSI design system (MFO), pp. 452–460.

DAC-1979-Waxman #challenge #design #named

VLSI — a design challenge (RW), pp. 546–547.

DAC-1979-Wiemann

CAD system for VLSI (WW), p. 550.

STOC-1979-Thompson #complexity

Area-Time Complexity for VLSI (CDT), pp. 81–88.