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Travelled to:
1 × USA
Collaborated with:
T.Kim
Talks about:
simultan (1) ground (1) buffer (1) assign (1) power (1) polar (1) minim (1) clock (1) size (1) nois (1)

Person: Hochang Jang

DBLP DBLP: Jang:Hochang

Contributed to:

DAC 20092009

Wrote 1 papers:

DAC-2009-JangK
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization (HJ, TK), pp. 794–799.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.