BibSLEIGH — Proceedings of the 46th Design Automation Conference

Proceedings of the 46th Design Automation Conference
DAC, 2009.

SYS

@proceedings{DAC-2009,
	acmid         = "1629911",
	address       = "San Francisco, California, USA",
	isbn          = "978-1-60558-497-3",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 46th Design Automation Conference}",
	year          = 2009,
}

Contents (193 items)

DAC-2009-BorgstromHWADCMCN #hardware #hybrid #prototype #question: System prototypes: virtual, hardware or hybrid? (TB, EH, RW, DA, AD, RC, OM, CC, AN), pp. 1–3.
DAC-2009-BowmanTWLKDB: Circuit techniques for dynamic variation tolerance (KAB, JT, CW, SLL, TK, VD, SYB), pp. 4–7.
DAC-2009-TuncerCL #adaptation: Enabling adaptability through elastic clocks (ET, JC, LL), pp. 8–10.
DAC-2009-DasBBFA #design: Addressing design margins through error-tolerant circuits (SD, DB, DMB, KF, RA), pp. 11–12.
DAC-2009-GandikotaDTB #modelling #worst-case: Worst-case aggressor-victim alignment with current-source driver models (RG, LD, PT, DB), pp. 13–18.
DAC-2009-LingVFA #analysis #effectiveness: A moment-based effective characterization waveform for static timing analysis (DDL, CV, PF, SA), pp. 19–24.
DAC-2009-TsaiH: A false-path aware formal static timing analyzer considering simultaneous input transitions (ST, CYH), pp. 25–30.
DAC-2009-KluterBIC #automation #set: Way Stealing: cache-assisted automatic instruction set extensions (TK, PB, PI, EC), pp. 31–36.
DAC-2009-WangHHW #framework #named #platform: SysCOLA: a framework for co-development of automotive software and system platform (ZW, AH, WH, MW), pp. 37–42.
DAC-2009-GlassLTBC #analysis #architecture #design #encoding #hybrid #network: Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis (MG, ML, JT, UDB, SC), pp. 43–46.
DAC-2009-LeeK #manycore #optimisation #throughput #using: Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating (JL, NSK), pp. 47–50.
DAC-2009-ThorolfssonGF #3d #automation #case study #design: Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study (TT, KG, PDF), pp. 51–56.
DAC-2009-PanKOMC #process: Selective wordline voltage boosting for caches to manage yield under process variations (YP, JK, SO, GM, SWC), pp. 57–62.
DAC-2009-YuanLP: Double patterning lithography friendly detailed routing with redundant via consideration (KY, KL, DZP), pp. 63–66.
DAC-2009-AbercrombiePC #design #equation #simulation #using: Use of lithography simulation for the calibration of equation-based design rule checks (DA, FP, CC), pp. 67–70.
DAC-2009-ZhangPHM: Carbon nanotube circuits in the presence of carbon nanotube density variations (JZ, NP, AH, SM), pp. 71–76.
DAC-2009-JamaaLM #array #multi: Decoding nanowire arrays fabricated with the multi-spacer patterning technique (MHBJ, YL, GDM), pp. 77–82.
DAC-2009-BawiecN #logic #synthesis: Boolean logic function synthesis for generalised threshold gate circuits (MAB, MN), pp. 83–86.
DAC-2009-XuCWZ: Improving STT MRAM storage density through smaller-than-worst-case transistor sizing (WX, YC, XW, TZ), pp. 87–90.
DAC-2009-HaritanKJERRG #question: EDA in flux: should I stay or should I go? (EH, AK, TJ, JE, JMR, RR, NG), pp. 91–92.
DAC-2009-Borkar #design: Design perspectives on 22nm CMOS and beyond (SB), pp. 93–94.
DAC-2009-StrojwasJRP #using: Creating an affordable 22nm node using design-lithography co-optimization (AJS, TJ, VR, LTP), pp. 95–96.
DAC-2009-RoyKG #interactive: Device/circuit interactions at 22nm technology node (KR, JPK, SKG), pp. 97–102.
DAC-2009-Anderson #complexity #design #risk management: Beyond innovation: dealing with the risks and complexity of processor design in 22nm (CJA), p. 103.
DAC-2009-ChengGSQH #modelling #variability: Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability (LC, PG, CJS, KQ, LH), pp. 104–109.
DAC-2009-TakahashiYT #analysis #statistics: A Gaussian mixture model for statistical timing analysis (ST, YY, ST), pp. 110–115.
DAC-2009-BurnhamYH #probability: A stochastic jitter model for analyzing digital timing-recovery circuits (JRB, CKKY, HAH), pp. 116–121.
DAC-2009-XiongVZ #correlation #ranking #statistics: Statistical ordering of correlated timing quantities and its application for path ranking (JX, CV, VZ), pp. 122–125.
DAC-2009-MutluLMC #analysis #approach #parametricity: A parametric approach for handling local variation effects in timing analysis (AAM, JL, RM, MC), pp. 126–129.
DAC-2009-ShankarL #multi #profiling: Non-intrusive dynamic application profiling for multitasked applications (KS, RLL), pp. 130–135.
DAC-2009-LaiYKH #performance #realtime: A trace-capable instruction cache for cost efficient real-time program trace compression in SoC (CHL, FCY, CFK, IJH), pp. 136–141.
DAC-2009-DangRMM #generative #interactive #pipes and filters #source code: Generating test programs to cover pipeline interactions (TND, AR, TM, PM), pp. 142–147.
DAC-2009-WenCCS #architecture #concurrent #debugging #detection #manycore #named: NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core (CNW, SHC, TFC, APS), pp. 148–153.
DAC-2009-VeetilSBSR #analysis #dependence #performance: Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence (VV, DS, DB, SS, SR), pp. 154–159.
DAC-2009-ArbelER: Resurrecting infeasible clock-gating functions (EA, CE, OR), pp. 160–165.
DAC-2009-WangCSC #graph #power management #synthesis #using: Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (RW, NCC, BS, CKC), pp. 166–171.
DAC-2009-WalravensVD #analysis #modelling #named #performance: ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models (CW, YV, WD), pp. 172–177.
DAC-2009-ShiCHMTHW #analysis #gpu #grid #network #performance #power management: GPU friendly fast Poisson solver for structured power grid network analysis (JS, YC, WH, LM, SXDT, PHH, XW), pp. 178–183.
DAC-2009-GhaniN #approximate #grid #performance #power management #using #verification: Fast vectorless power grid verification using an approximate inverse technique (NHAG, FNN), pp. 184–189.
DAC-2009-FeySD #bound #fault tolerance #using: Computing bounds for fault tolerance using formal techniques (GF, AS, RD), pp. 190–195.
DAC-2009-OnaissiHN #optimisation #process: Clock skew optimization via wiresizing for timing sign-off covering all process corners (SO, KRH, FNN), pp. 196–201.
DAC-2009-CongNPJBGRRS #question: Moore’s Law: another casualty of the financial meltdown? (JC, NSN, RP, WHJ, JB, MG, RR, PR, HS), pp. 202–203.
DAC-2009-Thaker #question #verification: Holistic verification: myth or magic bullet? (PAT), pp. 204–208.
DAC-2009-StapletonT #component #design #problem #reuse #verification: Verification problems in reusing internal design components (WS, PT), pp. 209–211.
DAC-2009-Whipp #architecture #process #verification: Exploiting “architecture for verification” to streamline the verification process (DW), pp. 212–215.
DAC-2009-Chesters #development #lifecycle #verification: Role of the verification team throughout the ASIC development life cycle (EC), pp. 216–219.
DAC-2009-WangH #approach #embedded #performance #simulation: An efficient approach for system-level timing simulation of compiler-optimized embedded software (ZW, AH), pp. 220–225.
DAC-2009-ZengYGP #manycore #named: MPTLsim: a simulator for X86 multicore processors (HZ, MTY, KG, DVP), pp. 226–231.
DAC-2009-IsshikiLKIS #multi #simulation: Trace-driven workload simulation method for Multiprocessor System-On-Chips (TI, DL, HK, TI, KS), pp. 232–237.
DAC-2009-LinB #analysis #process: Analysis and mitigation of process variation impacts on Power-Attack Tolerance (LL, WPB), pp. 238–243.
DAC-2009-BordoloiHCM #design #trade-off: Evaluating design trade-offs in customizable processors (UDB, HPH, SC, TM), pp. 244–249.
DAC-2009-JavaidP #design #multi #pipes and filters: A design flow for application specific heterogeneous pipelined multiprocessor systems (HJ, SP), pp. 250–253.
DAC-2009-ArfaeeILFK #linear #multi #named #performance: Xquasher: a tool for efficient computation of multiple linear expressions (AA, AI, NL, FF, RK), pp. 254–257.
DAC-2009-LinC #design: ILP-based pin-count aware design methodology for microfluidic biochips (CCYL, YWC), pp. 258–263.
DAC-2009-DingZHCP #framework #integration #named #power management: O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration (DD, YZ, HH, RTC, DZP), pp. 264–269.
DAC-2009-WilleD #logic #scalability #synthesis: BDD-based synthesis of reversible logic for large functions (RW, RD), pp. 270–275.
DAC-2009-PellauerACE #composition #problem: Soft connections: addressing the hardware-design modularity problem (MP, MA, DC, JSE), pp. 276–281.
DAC-2009-HagiescuWBR: A computing origami: folding streams in FPGAs (AH, WFW, DFB, RMR), pp. 282–287.
DAC-2009-BufistovCOJK #evaluation: Retiming and recycling for elastic systems with early evaluation (DB, JC, MGO, JJ, MK), pp. 288–291.
DAC-2009-OmsCK: Speculation in elastic systems (MGO, JC, MK), pp. 292–295.
DAC-2009-RedfordSSHZM #named #question: DFM: don’t care or competitive weapon? (MR, JS, PS, CH, YZ, KM), pp. 296–297.
DAC-2009-Welser #challenge #industrial #motivation #research: The semiconductor industry’s nanoelectronics research initiative: motivation and challenges (JW), pp. 298–300.
DAC-2009-Uchida #ubiquitous: Single-electron devices for ubiquitous and secure computing applications (KU), pp. 301–303.
DAC-2009-PatilLZWM #logic #using: Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions (NP, AL, JZ, HSPW, SM), pp. 304–309.
DAC-2009-Kuhn #challenge #scalability: CMOS scaling beyond 32nm: challenges and opportunities (KJK), pp. 310–313.
DAC-2009-LiuYKC #algorithm: An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction (CHL, SYY, SYK, YHC), pp. 314–319.
DAC-2009-WuDL #3d #integer #named #programming #scalability #using: GRIP: scalable 3D global routing using integer programming (THW, AD, JTL), pp. 320–325.
DAC-2009-KongYW #automation: Automatic bus planner for dense PCBs (HK, TY, MDFW), pp. 326–331.
DAC-2009-YanW #network: A correct network flow model for escape routing (TY, MDFW), pp. 332–335.
DAC-2009-FangWC #co-evolution #design: Flip-chip routing with unified area-I/O pad assignments for package-board co-design (JWF, MDFW, YWC), pp. 336–339.
DAC-2009-XiongSZV #multi #process #statistics: Statistical multilayer process space coverage for at-speed test (JX, YS, VZ, CV), pp. 340–345.
DAC-2009-CallegariWB #analysis #ranking: Speedpath analysis based on hypothesis pruning and ranking (NC, LCW, PB), pp. 346–351.
DAC-2009-LiuX #design #validation: Interconnection fabric design for tracing signals in post-silicon validation (XL, QX), pp. 352–357.
DAC-2009-VishnoiPB #debugging #online: Online cache state dumping for processor debug (AV, PRP, MB), pp. 358–363.
DAC-2009-Li #equation #modelling #performance #scalability: Finding deterministic solution from underdetermined equation: large-scale performance modeling by least angle regression (XL0), pp. 364–369.
DAC-2009-MehrotraS #performance #robust #using: A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian (AM, AS), pp. 370–375.
DAC-2009-KimRH #analysis #probability: Stochastic steady-state and AC analyses of mixed-signal systems (JK, JR, MAH), pp. 376–381.
DAC-2009-DongL #integration #performance #simulation: Parallelizable stable explicit numerical integration for efficient circuit simulation (WD, PL), pp. 382–385.
DAC-2009-ZhangCTL #performance #worst-case: Efficient design-specific worst-case corner extraction for integrated circuits (HZ, THC, MYT, XL), pp. 386–389.
DAC-2009-ChoudhuryM #logic #lookahead #optimisation #using: Timing-driven optimization using lookahead logic circuits (MRC, KM), pp. 390–395.
DAC-2009-WangCL #network #satisfiability #scalability #simulation: Simulation and SAT-based Boolean matching for large Boolean networks (KHW, CMC, JCL), pp. 396–401.
DAC-2009-ChenCH #design #information retrieval #order: New spare cell design for IR drop minimization in Engineering Change Order (HTC, CCC, TH), pp. 402–407.
DAC-2009-JiangCCH #design #low cost: Matching-based minimum-cost spare cell selection for design changes (IHRJ, HYC, LGC, HBH), pp. 408–411.
DAC-2009-ChouCK #synthesis: Handling don’t-care conditions in high-level synthesis and application for reducing initialized registers (HZC, KHC, SYK), pp. 412–415.
DAC-2009-GroeneveldRPCC: Oil fields, hedge funds, and drugs (PG, RAR, JWP, ECC, JC), pp. 416–417.
DAC-2009-Ahn: Human computation (LvA), pp. 418–419.
DAC-2009-George #how: How to make computers that work like the brain (DG), pp. 420–423.
DAC-2009-HuLA #approximate #polynomial: A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion (SH, ZL, CJA), pp. 424–429.
DAC-2009-JiangHCC #multi: Spare-cell-aware multilevel analytical placement (ZWJ, MKH, YWC, KYC), pp. 430–435.
DAC-2009-YanVC #scalability: Handling complexities in modern large-scale mixed-size placement (JZY, NV, CC), pp. 436–441.
DAC-2009-ChakrabortyKP #framework #named #open source #quality: RegPlace: a high quality open-source placement framework for structured ASICs (AC, AK, DZP), pp. 442–447.
DAC-2009-MarcilioSAR #behaviour #novel #verification: A novel verification technique to uncover out-of-order DUV behaviors (GM, LCVdS, BA, SR), pp. 448–453.
DAC-2009-GluskaL #modelling #verification: Shortening the verification cycle with synthesizable abstract models (AG, LL), pp. 454–459.
DAC-2009-ChauhanGHMS #equivalence: Non-cycle-accurate sequential equivalence checking (PC, DG, GH, AM, NS), pp. 460–465.
DAC-2009-GodlinS #verification: Regression verification (BG, OS), pp. 466–471.
DAC-2009-ZhangS #estimation #using: Accurate temperature estimation using noisy thermal sensors (YZ, AS), pp. 472–477.
DAC-2009-CochranR: Spectral techniques for high-resolution thermal characterization with limited sensor data (RC, SR), pp. 478–483.
DAC-2009-JayaseelanM #adaptation #architecture: Dynamic thermal management via architectural adaptation (RJ, TM), pp. 484–489.
DAC-2009-BaoAEP #dependence #energy #online #optimisation #scalability: On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration (MB, AA, PE, ZP), pp. 490–495.
DAC-2009-WangYLP #analysis #parametricity: SRAM parametric failure analysis (JW, SY, XL, LTP), pp. 496–501.
DAC-2009-ShengXM #algorithm #fault #multi #optimisation #search-based #standard: Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm (WS, LX, ZM), pp. 502–507.
DAC-2009-KrishnaswamyMH #testing: Improving testability and soft-error resilience through retiming (SK, ILM, JPH), pp. 508–513.
DAC-2009-LuSZZYZ #analysis #process #reliability #statistics: Statistical reliability analysis under process variation and aging effects (YL, LS, HZ, HZ, FY, XZ), pp. 514–519.
DAC-2009-YingKKGGOTW #how #question: Guess, solder, measure, repeat: how do I get my mixed-signal chip right? (GY, AK, KSK, GGEG, EG, MO, ST, WW), pp. 520–521.
DAC-2009-Leiserson #concurrent #framework #platform: The Cilk++ concurrency platform (CEL), pp. 522–527.
DAC-2009-Bailey #parallel #performance: Misleading performance claims in parallel computations (DHB), pp. 528–533.
DAC-2009-LevitanC #parallel: Massively parallel processing: it’s déjà vu all over again (SPL, DMC), pp. 534–538.
DAC-2009-FengZYTZ #algorithm #performance: Provably good and practically efficient algorithms for CMP dummy fill (CF, HZ, CY, JT, XZ), pp. 539–544.
DAC-2009-DrmanacLW #predict #process #variability: Predicting variability in nanoscale lithography processes (DGD, FL, LCW), pp. 545–550.
DAC-2009-YeLCC #analysis #layout #process #variability: Variability analysis under layout pattern-dependent rapid-thermal annealing process (YY, FL, MC, YC), pp. 551–556.
DAC-2009-ChatterjeeDB #simulation: Event-driven gate-level simulation with GP-GPUs (DC, AD, VB), pp. 557–562.
DAC-2009-JainC #graph #performance #satisfiability #using: Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts (HJ, EMC), pp. 563–568.
DAC-2009-NanshiS #abstraction #constraints #refinement: Constraints in one-to-many concretization for abstraction refinement (KN, FS), pp. 569–574.
DAC-2009-LiFMSVFPS #hybrid #named #network: Spectrum: a hybrid nanophotonic-electric on-chip network (ZL, DF, ARM, LS, MV, DF, WP, YS), pp. 575–580.
DAC-2009-Pasricha #3d: Exploring serial vertical interconnects for 3D ICs (SP), pp. 581–586.
DAC-2009-ChouCWCCWW #3d #manycore: No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips (SHC, CCC, CNW, YCC, TFC, CCW, JSW), pp. 587–592.
DAC-2009-LinZWC: Thermal-driven analog placement considering device matching (MPHL, HZ, MDFW, YWC), pp. 593–598.
DAC-2009-LiS #algorithm #optimisation #robust: Yield-driven iterative robust circuit optimization algorithm (YL, VS), pp. 599–604.
DAC-2009-SunNWS #composition #contract: Contract-based system-level composition of analog circuits (XS, PN, CCW, ALSV), pp. 605–610.
DAC-2009-ChattopadhyayZ #configuration management: Serial reconfigurable mismatch-tolerant clock distribution (AC, ZZ), pp. 611–612.
DAC-2009-AyalaAB #analysis #data flow: Thermal-aware data flow analysis (JLA, DA, PB), pp. 613–614.
DAC-2009-AltunRN: Nanoscale digital computation through percolation (MA, MDR, CN), pp. 615–616.
DAC-2009-MarrBBH #learning: A learning digital computer (BM, AB, SB, PEH), pp. 617–618.
DAC-2009-HuangOSC #programmable: Programmable neural processing on a smartdust (SH, JO, YS, ACC), pp. 619–620.
DAC-2009-DeOrioB: Human computing for EDA (AD, VB), pp. 621–622.
DAC-2009-RaabeB #hardware #sketching: Synthesizing hardware from sketches (AR, RB), pp. 623–624.
DAC-2009-Chou #cyber-physical #user interface: Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity (PHC), pp. 625–626.
DAC-2009-FujitaKG #debugging: Debugging from high level down to gate level (MF, YK, AMG), pp. 627–630.
DAC-2009-VenerisS: The day Sherlock Holmes decided to do EDA (AGV, SS), pp. 631–634.
DAC-2009-Bertacco #debugging: Debugging strategies for mere mortals (VB), pp. 635–638.
DAC-2009-KamhiNTW #analysis #architecture #named #statistics #transaction: MAGENTA: transaction-based statistical micro-architectural root-cause analysis (GK, AN, AT, AW), pp. 639–643.
DAC-2009-SiegelMP #debugging #performance: Untwist your brain: efficient debugging and diagnosis of complex assertions (MS, AM, CP), pp. 644–647.
DAC-2009-RanjanCS #debugging #verification: Beyond verification: leveraging formal for debugging (RKR, CC, SS), pp. 648–651.
DAC-2009-DongCZ #modelling #user interface #visual notation: Power modeling of graphical user interfaces on OLED displays (MD, YSKC, LZ), pp. 652–657.
DAC-2009-PapirlaC #energy #fault: Energy-aware error control coding for Flash memories (VP, CC), pp. 658–663.
DAC-2009-DhimanAR #hybrid #in memory #memory management #named: PDRAM: a hybrid PRAM and DRAM main memory system (GD, RZA, TR), pp. 664–469.
DAC-2009-ChangMR #architecture #hybrid #process #video: A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors (IJC, DM, KR), pp. 670–675.
DAC-2009-HelinskiAP #physics #using: A physical unclonable function defined using power distribution system equivalent resistance variations (RH, DA, JP), pp. 676–681.
DAC-2009-DengCS #authentication #hardware #performance #simulation: Hardware authentication leveraging performance limits in detailed simulations and emulations (DYD, AHC, GES), pp. 682–687.
DAC-2009-PotkonjakNNM #detection #hardware #using: Hardware Trojan horse detection using gate-level characterization (MP, AN, MN, TM), pp. 688–693.
DAC-2009-ZhangBDSJ #multi #process: Process variation characterization of chip-level multiprocessors (LZ, LSB, RPD, LS, RJ), pp. 694–697.
DAC-2009-GuQZ #design #information management: Information hiding for trusted system design (JG, GQ, QZ), pp. 698–701.
DAC-2009-YuanX #identification #on the #pseudo #testing: On systematic illegal state identification for pseudo-functional testing (FY, QX), pp. 702–707.
DAC-2009-TamPB #automation #validation: Automated failure population creation for validating integrated circuit diagnosis methods (WCT, OP, RD(B), pp. 708–713.
DAC-2009-ChaoYHLC #fault #metaprogramming #modelling: Fault models for embedded-DRAM macros (MCTC, HYY, RFH, SCL, CYC), pp. 714–719.
DAC-2009-YilmazO #adaptation: Adaptive test elimination for analog/RF circuits (EY, SO), pp. 720–725.
DAC-2009-Falk #graph: WCET-aware register allocation based on graph coloring (HF), pp. 726–731.
DAC-2009-FalkK: Optimal static WCET-aware scratchpad allocation of program code (HF, JCK), pp. 732–737.
DAC-2009-UzelacM #realtime: A real-time program trace compressor utilizing double move-to-front method (VU, AM), pp. 738–743.
DAC-2009-BaiocchiC #in memory #memory management #using: Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators (JB, BRC), pp. 744–749.
DAC-2009-PuriHKCKMST #challenge: From milliwatts to megawatts: system level power challenge (RP, EH, SK, JC, TK, BDM, JS, AT), pp. 750–751.
DAC-2009-ChaiJK #3d #complexity #equation #linear #scalability: A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction (WC, DJ, CKK), pp. 752–757.
DAC-2009-YuHZ: Variational capacitance extraction of on-chip interconnects based on continuous surface model (WY, CH, WZ), pp. 758–763.
DAC-2009-GongYH #incremental #named #parallel #probability #process: PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation (FG, HY, LH), pp. 764–769.
DAC-2009-El-MoselhyED #algorithm #performance: An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapes (TAEM, IME, BD), pp. 770–775.
DAC-2009-HanumaiahRVC #constraints #manycore #throughput: Throughput optimal task allocation under thermal constraints for multi-core processors (VH, RR, SBKV, KSC), pp. 776–781.
DAC-2009-LiuWQ #adaptation #algorithm #energy #realtime #scheduling: An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems (SL, QW, QQ), pp. 782–787.
DAC-2009-ReddiGSWBC #challenge #hardware #reliability #stack: Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack (VJR, SC, MSG, MDS, GYW, DMB), pp. 788–793.
DAC-2009-JangK: Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization (HJ, TK), pp. 794–799.
DAC-2009-JangP: An SDRAM-aware router for Networks-on-Chip (WJ, DZP), pp. 800–805.
DAC-2009-YooYC #design #memory management #multi #performance: Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency (JhY, SY, KC), pp. 806–811.
DAC-2009-FickDHBBS #named #network #reliability: Vicis: a reliable network for unreliable silicon (DF, AD, JH, VB, DB, DS), pp. 812–817.
DAC-2009-GargMMO #design #multi #perspective: Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective (SG, DM, RM, ÜYO), pp. 818–821.
DAC-2009-SeiculescuMBM #synthesis: NoC topology synthesis for supporting shutdown of voltage islands in SoCs (CS, SM, LB, GDM), pp. 822–825.
DAC-2009-KimM #array #configuration management #embedded #performance: Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems (YK, RNM), pp. 826–831.
DAC-2009-LuZSZ #algorithm #manycore #parallel: Multicore parallel min-cost flow algorithm for CAD applications (YL, HZ, LS, XZ), pp. 832–837.
DAC-2009-CromarLC #algorithm #reduction: FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation (SC, JL, DC), pp. 838–843.
DAC-2009-AlimohammadFC #verification: FPGA-based accelerator for the verification of leading-edge wireless systems (AA, SFF, BFC), pp. 844–847.
DAC-2009-HuangV: Transmuting coprocessors: dynamic loading of FPGA coprocessors (CH, FV), pp. 848–851.
DAC-2009-KandemirOM #concurrent #thread: Dynamic thread and data mapping for NoC based CMPs (MTK, ÖÖ, SPM), pp. 852–857.
DAC-2009-ChangK #performance #reliability: A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems (YHC, TWK), pp. 858–863.
DAC-2009-SamiiEPC #embedded #multi #quality #synthesis: Quality-driven synthesis of embedded multi-mode control systems (SS, PE, ZP, AC), pp. 864–869.
DAC-2009-JuHCR #analysis #source code: Context-sensitive timing analysis of Esterel programs (LJ, BKH, SC, AR), pp. 870–873.
DAC-2009-ZengZNGGS #optimisation #scheduling #using: Scheduling the FlexRay bus using optimization techniques (HZ, WZ, MDN, AG, PG, ALSV), pp. 874–877.
DAC-2009-YagiREAVS #design: The wild west: conquest of complex hardware-dependent software design (HY, WR, JE, JA, KAV, MS), pp. 878–879.
DAC-2009-EllithorpeTK #architecture #named #network #using: Internet-in-a-Box: emulating datacenter network architectures using FPGAs (JDE, ZT, RHK), pp. 880–883.
DAC-2009-BanerjeePBR: Sustainable data centers: enabled by supply and demand side management (PB, CDP, CB, PR), pp. 884–887.
DAC-2009-KandlurK: Green data centers and hot chips (DDK, TWK), pp. 888–890.
DAC-2009-AmadorPR #architecture #memory management #problem: Optimum LDPC decoder: a memory architecture problem (EA, RP, VR), pp. 891–896.
DAC-2009-GeMW #configuration management #memory management #pipes and filters: A DVS-based pipelined reconfigurable instruction memory (ZG, TM, WFW), pp. 897–902.
DAC-2009-BonnyH #named #performance: LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors (TB, JH), pp. 903–906.
DAC-2009-JungKS #architecture #performance: Hierarchical architecture of flash-based storage systems for high performance and durability (SJ, JHK, YHS), pp. 907–910.
DAC-2009-Geilen #data flow #graph #reduction: Reduction techniques for synchronous dataflow graphs (MG), pp. 911–916.
DAC-2009-ShojaeiGBGSH #composition #heuristic #multi #runtime: A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management (HS, AHG, TB, MG, SS, RH), pp. 917–922.
DAC-2009-PlishkerSB #data flow #effectiveness #scheduling: Mode grouping for more effective generalized scheduling of dynamic dataflow applications (WP, NS, SSB), pp. 923–926.
DAC-2009-ChenJ #manycore #performance #scheduling: Efficient program scheduling for heterogeneous multi-core processors (JC, LKJ), pp. 927–930.
DAC-2009-SarbisheiAF #clustering #heuristic #optimisation #polynomial #using: Polynomial datapath optimization using partitioning and compensation heuristics (OS, BA, MF), pp. 931–936.
DAC-2009-ShinPS #synthesis #using: Register allocation for high-level synthesis using dual supply voltages (IS, SP, YS), pp. 937–942.
DAC-2009-LiuH #optimisation #parallel #performance: GPU-based parallelization for fast circuit optimization (YL, JH), pp. 943–946.
DAC-2009-BaumannSP #architecture #assessment #design #embedded #robust: Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors (TB, DSL, CP), pp. 947–950.
DAC-2009-VillenaS #automation #modelling #multi #named: ARMS — automatic residue-minimization based sampling for multi-point modeling techniques (JFV, LMS), pp. 951–956.
DAC-2009-Wong #canonical #performance: An efficient passivity test for descriptor systems via canonical projector techniques (NW), pp. 957–962.
DAC-2009-Zhu #simulation: A parameterized mask model for lithography simulation (ZZ), pp. 963–968.

Proceedings of the 46th Design Automation ConferenceDAC, 2009.

Contents (193 items)

Proceedings of the 46th Design Automation Conference
DAC, 2009.