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Travelled to:
1 × Germany
1 × Italy
Collaborated with:
Y.Chen J.Huang Y.Tseng F.Huang
Talks about:
transistor (1) reconfigur (1) constraint (1) synthesi (1) electron (1) approach (1) support (1) sequenc (1) assembl (1) system (1)

Person: Jian-Yu Chen

DBLP DBLP: Chen:Jian=Yu

Contributed to:

DATE 20142014
ICEIS AIDSS 20092009

Wrote 2 papers:

DATE-2014-ChenCH #array #configuration management #constraints #synthesis
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints (YHC, JYC, JDH), pp. 1–4.
ICEIS-AIDSS-2009-TsengCH #approach #assembly #multi #sequence #using
A Decision Support System for Multi-plant Assembly Sequence Planning using a PSO Approach (YJT, JYC, FYH), pp. 124–129.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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