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Travelled to:
1 × France
Collaborated with:
S.A.Butt S.Schmermbeck A.Pratsch E.Schmidt
Talks about:
synthesi (1) system (1) power (1) optim (1) level (1) clock (1) tree (1)

Person: Jurij Rosenthal

DBLP DBLP: Rosenthal:Jurij

Contributed to:

DATE 20072007

Wrote 1 papers:

DATE-2007-ButtSRPS #optimisation #synthesis
System level clock tree synthesis for power optimization (SAB, SS, JR, AP, ES), pp. 1677–1682.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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