BibSLEIGH — Proceedings of the 11th Conference on Design, Automation and Test in Europe

Rudy Lauwereins, Jan Madsen
Proceedings of the 11th Conference on Design, Automation and Test in Europe
DATE, 2007.

SYS

@proceedings{DATE-2007,
	address       = "Nice, France",
	editor        = "Rudy Lauwereins and Jan Madsen",
	isbn          = "978-3-9810801-2-4",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 11th Conference on Design, Automation and Test in Europe}",
	year          = 2007,
}

Contents (292 items)

DATE-2007-Furuyama #challenge #mobile #question: Keynote address: Challenges of digital consumer and mobile SoC’s: more Moore possible? (TF), p. 1.
DATE-2007-Naumann #design #evolution #question: Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore’s law? (AN), p. 2.
DATE-2007-NjorogeCWTGKO #memory management #multi #named #transaction: ATLAS: a chip-multiprocessor with transactional memory support (NN, JC, SW, YT, DG, CK, KO), pp. 3–8.
DATE-2007-CampiDPCRMLVV #adaptation #configuration management #platform: A dynamically adaptive DSP for heterogeneous reconfigurable platforms (FC, AD, MP, LC, PLR, CM, AL, AV, LV), pp. 9–14.
DATE-2007-Stanley-MarbellM #communication #energy #interface #multi #power management: An 0.9 × 1.2”, low power, energy-harvesting system with custom multi-channel communication interface (PSM, DM), pp. 15–20.
DATE-2007-YeGM #interactive: Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio (ZY, JG, GM), pp. 21–26.
DATE-2007-SinanogluP #approach: A non-intrusive isolation approach for soft cores (OS, TP), pp. 27–32.
DATE-2007-WangWC: Unknown blocking scheme for low control data volume and high observability (SW, WW, STC), pp. 33–38.
DATE-2007-ZhouB #approach #reduction #scheduling #testing #using: Test cost reduction for SoC using a combined approach to test data compression and test scheduling (QZ, KJB), pp. 39–44.
DATE-2007-WangY #fault #synthesis #testing: High-level test synthesis for delay fault testability (SJW, THY), pp. 45–50.
DATE-2007-PopPEP #distributed #embedded #optimisation: Bus access optimisation for FlexRay-based distributed embedded systems (TP, PP, PE, ZP), pp. 51–56.
DATE-2007-SatishRK #approach #communication #constraints #graph #multi #optimisation #scheduling: A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors (NS, KR, KK), pp. 57–62.
DATE-2007-LinXZ #design #network: Design closure driven delay relaxation based on convex cost network flow (CL, AX, HZ), pp. 63–68.
DATE-2007-AggarwalO #modelling #parametricity #reuse: Simulation-based reusable posynomial models for MOS transistor parameters (VA, UMO), pp. 69–74.
DATE-2007-MuellerGS #design #polynomial #programming #trade-off #using: Trade-off design of analog circuits using goal attainment and “Wave Front” sequential quadratic programming (DM, HEG, US), pp. 75–80.
DATE-2007-EeckelaertSGSS #performance #synthesis: An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection (TE, RS, GGEG, MS, WMCS), pp. 81–86.
DATE-2007-YetikSTD #architecture #interactive #matlab #optimisation: Interactive presentation: A coefficient optimization and architecture selection tool for SigmaDelta modulators in MATLAB (ÖY, OS, ST, GD), pp. 87–92.
DATE-2007-ZhengNPGV #distributed #modelling #realtime #synthesis: Synthesis of task and message activation models in real-time distributed automotive systems (WZ, MDN, CP, PG, ALSV), pp. 93–98.
DATE-2007-OstlerC #architecture #network: An ILP formulation for system-level application mapping on network processor architectures (CO, KSC), pp. 99–104.
DATE-2007-DestroFP #refinement #thread: A smooth refinement flow for co-designing HW and SW threads (PD, FF, GP), pp. 105–110.
DATE-2007-NaguibG #process #simulation: Speeding up SystemC simulation through process splitting (YNN, RSG), pp. 111–116.
DATE-2007-KumarHHC #configuration management #design #interactive #multi: Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip (AK, AH, JH, HC), pp. 117–122.
DATE-2007-DittmannF #configuration management #realtime #scheduling: Hard real-time reconfiguration port scheduling (FD, SF), pp. 123–128.
DATE-2007-CuiDHG #2d #algorithm #configuration management #online #performance: An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs (JC, QD, XH, ZG), pp. 129–134.
DATE-2007-FaragES #2d #configuration management #using: Improving utilization of reconfigurable resources using two dimensional compaction (AAEF, HMEB, SIS), pp. 135–140.
DATE-2007-Lysecky #embedded #performance #power management: Low-power warp processor for power efficient high-performance embedded systems (RLL), pp. 141–146.
DATE-2007-QuSN #configuration management #energy #interactive #runtime #scalability #using: Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices (YQ, JPS, JN), pp. 147–152.
DATE-2007-SafarSES #configuration management #interactive #satisfiability: Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver (MS, MS, MWEK, AS), pp. 153–158.
DATE-2007-PapadonikolakisPK #implementation #performance: Efficient high-performance ASIC implementation of JPEG-LS encoder (MEP, VP, AK), pp. 159–164.
DATE-2007-ChangLR #performance #using: Improve CAM power efficiency using decoupled match line scheme (YJC, YHL, SJR), pp. 165–170.
DATE-2007-KokkelerSKK #detection: Cyclostationary feature detection on a tiled-SoC (ABJK, GJMS, TK, JK), pp. 171–176.
DATE-2007-ArbeloKLLBSM #architecture #configuration management #kernel #video: Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter (CA, AK, SL, JFL, MB, RS, JYM), pp. 177–182.
DATE-2007-SahinH #algorithm #architecture #hardware #interactive #performance #predict: Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm (ES, IH), pp. 183–188.
DATE-2007-NarayananHMCZ #classification #implementation #interactive: Interactive presentation: An FPGA implementation of decision tree classification (RN, DH, GM, ANC, JZ), pp. 189–194.
DATE-2007-Srivastava #interactive #predict #scalability: Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling (NRS), pp. 195–200.
DATE-2007-WangCW #optimisation #scheduling #testing #using: SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling (ZW, KC, SW), pp. 201–206.
DATE-2007-LarssonLEP #integration #testing: Optimized integration of test compression and sharing for SOC testing (AL, EL, PE, ZP), pp. 207–212.
DATE-2007-SpangSW #memory management: A sophisticated memory test engine for LCD display drivers (OS, HMvS, MGW), pp. 213–218.
DATE-2007-LeGB #pervasive #verification: Formal verification of a pervasive interconnect bus system in a high-performance microprocessor (TL, TG, JB), pp. 219–224.
DATE-2007-AnisN #architecture #debugging #interactive #low cost #using: Interactive presentation: Low cost debug architecture using lossy compression for silicon debug (EA, NN), pp. 225–230.
DATE-2007-YonedaIF #algorithm #configuration management #interactive #scheduling #using: Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers (TY, MI, HF), pp. 231–236.
DATE-2007-BorkarJS #integration: Microprocessors in the era of terascale integration (SB, NPJ, PS), pp. 237–242.
DATE-2007-ZhangOSFKB #analysis #approach #named #parametricity #process: CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions (MZ, MO, DS, MF, HK, EB), pp. 243–248.
DATE-2007-Al-SammaneZT #design #verification: A symbolic methodology for the verification of analog and mixed signal designs (GAS, MHZ, ST), pp. 249–254.
DATE-2007-TannirK #analysis #performance: Efficient nonlinear distortion analysis of RF circuits (DT, RK), pp. 255–260.
DATE-2007-BorremansLWR #analysis #multi #using: Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis (JB, LDL, PW, YR), pp. 261–266.
DATE-2007-LataireVP #design #interactive #multi #optimisation #using: Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations (JL, GV, RP), pp. 267–272.
DATE-2007-SchlieckerSE #analysis #composition #data flow #graph #integration #performance: Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis (SS, SS, RE), pp. 273–278.
DATE-2007-PatelS #abstraction: Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL (HDP, SKS), pp. 279–284.
DATE-2007-GeilenB: A calculator for Pareto points (MG, TB), pp. 285–290.
DATE-2007-HuangMW #design #modelling #simulation: Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer (SH, HM, ZW), pp. 291–296.
DATE-2007-GongW #interactive #optimisation: Interactive presentation: System level power optimization of Sigma-Delta modulator (FG, XW), pp. 297–300.
DATE-2007-IndrusiakTG #behaviour #execution #interactive #modelling #specification #uml: Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns (LSI, AT, MG), pp. 301–306.
DATE-2007-EachempatiNGVM #architecture: Assessing carbon nanotube bundle interconnect for future FPGA architectures (SE, AN, AG, NV, YM), pp. 307–312.
DATE-2007-SirowyWLV #clustering: Two-level microprocessor-accelerator partitioning (SS, YW, SL, FV), pp. 313–318.
DATE-2007-ChattopadhyayAKKLAM #configuration management #design #embedded: Design space exploration of partially re-configurable embedded processors (AC, WA, KK, DK, RL, GA, HM), pp. 319–324.
DATE-2007-NooriMMIG #adaptation #generative #interactive #multi: Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor (HN, FM, KM, KI, MG), pp. 325–330.
DATE-2007-BrackALKWLRRF #complexity #generative #standard: Low complexity LDPC code decoders for next generation standards (TB, MA, TLE, FK, NW, NEL, FR, MR, LF), pp. 331–336.
DATE-2007-DielissenH #implementation #parallel: Non-fractional parallelism in LDPC decoder implementations (JD, AH), pp. 337–342.
DATE-2007-WangC #energy #mobile #realtime: Minimum-energy LDPC decoder for real-time mobile application (WW, GC), pp. 343–348.
DATE-2007-KhanA #architecture #configuration management #implementation #pipes and filters #programmable #realtime: Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture (ZK, TA), pp. 349–354.
DATE-2007-MucciVCT #architecture #configuration management #implementation #interactive: Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture (CM, LV, FC, MT), pp. 355–360.
DATE-2007-HosseinabadyDN #testing #using: Using the inter- and intra-switch regularity in NoC switch testing (MH, AD, ZN), pp. 361–366.
DATE-2007-PetersenO #2d #scalability #towards: Toward a scalable test methodology for 2D-mesh Network-on-Chips (KP, JÖ), pp. 367–372.
DATE-2007-LaouamriA #framework #network #testing #using: Remote testing and diagnosis of System-on-Chips using network management frameworks (OL, CA), pp. 373–378.
DATE-2007-HuVKCP #dependence #estimation #memory management #performance: Fast memory footprint estimation based on maximal dependency vector calculation (QH, AV, PGK, FC, MP), pp. 379–384.
DATE-2007-ZhuLB #memory management #multi: Mapping multi-dimensional signals into hierarchical memory organizations (HZ, IIL, FB), pp. 385–390.
DATE-2007-KurraSP #synthesis: The impact of loop unrolling on controller delay in high level synthesis (SK, NKS, PRP), pp. 391–396.
DATE-2007-SirowyWLV07a #multi: Clock-frequency assignment for multiple clock domain systems-on-a-chip (SS, YW, SL, FV), pp. 397–402.
DATE-2007-GargM #analysis #design #interactive #multi #process #throughput: Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs (SG, DM), pp. 403–408.
DATE-2007-GlassLSHT #interactive #synthesis: Interactive presentation: Reliability-aware system synthesis (MG, ML, TS, CH, JT), pp. 409–414.
DATE-2007-SunWD #configuration management #design: Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators (PS, YW, AD), pp. 415–420.
DATE-2007-MatarreseMCDB #algorithm #performance #validation: Experimental validation of a tuning algorithm for high-speed filters (GM, CM, FC, SD, AB), pp. 421–426.
DATE-2007-AminzadehDL #design #pipes and filters: Design of high-resolution MOSFET-only pipelined ADCs with digital calibration (HA, MD, RL), pp. 427–432.
DATE-2007-SavojAAGH #performance: A new technique for characterization of digital-to-analog converters in high-speed systems (JS, AAA, AA, BWG, MAH), pp. 433–438.
DATE-2007-Casale-RossiSADGMPS #named #product line #question #trust: DFM/DFY: should you trust the surgeon or the family doctor? (MCR, AJS, RCA, AD, CG, PM, DP, JS), pp. 439–442.
DATE-2007-VermaI #automation #scalability #synthesis: Automatic synthesis of compressor trees: reevaluating large counters (AKV, PI), pp. 443–448.
DATE-2007-MolinaRMH #multi #optimisation #synthesis: Area optimization of multi-cycle operators in high-level synthesis (MCM, RRS, JMM, RH), pp. 449–454.
DATE-2007-CiesielskiAGGB #data flow #diagrams #using: Data-flow transformations using Taylor expansion diagrams (MJC, SA, DGP, JG, EB), pp. 455–460.
DATE-2007-ChongP #automation #float #generative: Automatic application specific floating-point unit generation (YJC, SP), pp. 461–466.
DATE-2007-Scholzel #clustering #interactive: Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP (MS), pp. 467–472.
DATE-2007-X #ubiquitous: Applications for ubiquitous computing and communications, p. 473.
DATE-2007-KrauseBHTR #component #simulation: Timing simulation of interconnected AUTOSAR software-components (MK, OB, AH, GT, WR), pp. 474–479.
DATE-2007-SaponaraPTCF #network #reliability: FPGA-based networking systems for high data-rate and reliable in-vehicle communications (SS, EP, MT, IDC, LF), pp. 480–485.
DATE-2007-DAscoliIMMTFGRM #performance #prototype: Low-g accelerometer fast prototyping for automotive applications (FD, FI, CM, MM, MT, LF, AG, AR, MDM), pp. 486–491.
DATE-2007-MarianiBC #design #using: Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508 (RM, GB, FC), pp. 492–497.
DATE-2007-ClausZMS #configuration management #hardware #using #video: Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system (CC, JZ, FHM, WS), pp. 498–503.
DATE-2007-PoppNGKP #architecture #evaluation #interactive #towards: Interactive presentation: Towards a methodology for the quantitative evaluation of automotive architectures (PP, MDN, PG, SK, CP), pp. 504–509.
DATE-2007-Huang #learning: Dynamic learning based scan chain diagnosis (YH0), pp. 510–515.
DATE-2007-SinanogluS #modelling: Diagnosis, modeling and tolerance of scan chain hold-time violations (OS, PS), pp. 516–521.
DATE-2007-PomeranzR #generative #on the #testing: On test generation by input cube avoidance (IP, SMR), pp. 522–527.
DATE-2007-NeyGLPVB #analysis #fault: Slow write driver faults in 65nm SRAM technology: analysis and March test solution (AN, PG, CL, SP, AV, MB), pp. 528–533.
DATE-2007-DevanathanRK #generative #interactive #testing: Interactive presentation: On power-profiling and pattern generation for power-safe scan tests (VRD, CPR, VK), pp. 534–539.
DATE-2007-GaneshpureK #automation #fault #generative #interactive #multi: Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults (KPG, SK), pp. 540–545.
DATE-2007-WangLHLYX #modelling #performance: Temperature-aware NBTI modeling and the impact of input vector control on performance degradation (YW, HL, KH, RL, HY, YX), pp. 546–551.
DATE-2007-XuC #array: A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays (TX, KC), pp. 552–557.
DATE-2007-ZilicRK #specification: Reversible circuit technology mapping from non-reversible specifications (ZZ, KR, AK), pp. 558–563.
DATE-2007-ZamoraKM #distributed #network #video: Distributed power-management techniques for wireless network video systems (NHZ, JCK, RM), pp. 564–569.
DATE-2007-AngioliniJABM #design #fault tolerance #interactive: Interactive presentation: Improving the fault tolerance of nanometric PLA designs (FA, MHBJ, DA, LB, GDM), pp. 570–575.
DATE-2007-NepalBMPZ #design #interactive #multi: Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits (KN, RIB, JLM, WRP, AZ), pp. 576–581.
DATE-2007-SeongM #performance #taxonomy #using: An efficient code compression technique using application-aware bitmask and dictionary selection methods (SWS, PM), pp. 582–587.
DATE-2007-AtasuDMLOD #constraints #optimisation: Optimizing instruction-set extensible processors under data bandwidth constraints (KA, RGD, OM, WL, CCÖ, GD), pp. 588–593.
DATE-2007-HamersE #predict: Resource prediction for media stream decoding (JH, LE), pp. 594–599.
DATE-2007-ParkPBBKD #architecture #embedded #performance #pointer: Register pointer architecture for efficient embedded processors (JP, SBP, JDB, DBS, CK, WJD), pp. 600–605.
DATE-2007-HaastregtK #interactive #optimisation #performance #random #using: Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search (SvH, PMWK), pp. 606–611.
DATE-2007-MilidonisAPMKG #architecture #interactive #memory management: Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy (AM, NA, VP, HM, AK, CEG), pp. 612–617.
DATE-2007-JayakumarK #algorithm: An algorithm to minimize leakage through simultaneous input vector control and circuit modification (NJ, SPK), pp. 618–623.
DATE-2007-GuptaOJWB #comprehension #distributed #multi #network #using: Understanding voltage variations in chip multiprocessors using a distributed power-delivery network (MSG, JLO, RJ, GYW, DMB), pp. 624–629.
DATE-2007-BanerjeeKR #architecture #power management #process: Process variation tolerant low power DCT architecture (NB, GK, KR), pp. 630–635.
DATE-2007-LinH #interactive #reduction #statistics: Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction (YL, LH), pp. 636–641.
DATE-2007-NaculRL #architecture #hardware #scheduling: Hardware scheduling support in SMP architectures (ACN, FR, ML), pp. 642–647.
DATE-2007-BjerregaardSS #architecture #scalability: A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method (TB, MBS, JS), pp. 648–653.
DATE-2007-MoussaMBJ #communication #multi #network: Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding (HM, OM, AB, MJ), pp. 654–659.
DATE-2007-MedardoniRBBSP #communication #in memory #industrial #interactive #memory management #platform: Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms (SM, MR, DB, LB, GS, CP), pp. 660–665.
DATE-2007-SuhonenKKHH #capacity #cost analysis #multi #optimisation: Cost-aware capacity optimization in dynamic multi-hop WSNs (JS, MK, MK, MH, TDH), pp. 666–671.
DATE-2007-VerbauwhedeS #design #security #trust: Design methods for security and trust (IV, PS), pp. 672–677.
DATE-2007-Huomo #communication #ubiquitous: Emerging solutions technology and business views for the ubiquitous communication (HH), p. 678.
DATE-2007-BaguenaLBDOBH #development #flexibility #generative: Development of on board, highly flexible, Galileo signal generator ASIC (LB, EL, AB, JMD, CO, PB, VH), pp. 679–683.
DATE-2007-HairionECS #design #safety: New safety critical radio altimeter for airbus and related design flow (DH, SE, EC, MS), pp. 684–688.
DATE-2007-LisselGG #design #industrial #perspective #verification: Introducing new verification methods into a company’s design flow: an industrial user’s point of view (RL, JG), pp. 689–694.
DATE-2007-LinC #design: Testable design for advanced serial-link transceivers (ML, KT(C), pp. 695–700.
DATE-2007-KeezerMD #multi: Method for reducing jitter in multi-gigahertz ATE (DCK, DM, PD), pp. 701–706.
DATE-2007-AndersKG #effectiveness #testing: Re-configuration of sub-blocks for effective application of time domain tests (JA, SK, GG), pp. 707–712.
DATE-2007-ErdoganO #analysis #using: An ADC-BiST scheme using sequential code analysis (ESE, SO), pp. 713–718.
DATE-2007-DabrowskiR #interactive: Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique (JD, RR), pp. 719–724.
DATE-2007-YeungTB #framework #interactive #interface #multi #novel: Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor (PY, AT, PB), pp. 725–730.
DATE-2007-TongbongMC #evaluation #interactive #metric #multi #statistics #testing #using: Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model (JT, SM, JLC), pp. 731–736.
DATE-2007-OConnorCCDHH: Heterogeneous systems on chip and systems in package (IO, BC, KC, ND, MH, JH), pp. 737–742.
DATE-2007-WagnerB #semantics #trust: Engineering trust with semantic guardians (IW, VB), pp. 743–748.
DATE-2007-KimHG #multi #named #simulation #transaction: CATS: cycle accurate transaction-driven simulation with multiple processor simulators (DK, SH, RG), pp. 749–754.
DATE-2007-Gordon-RossVVNB #configuration management #energy #performance: A one-shot configurable-cache tuner for improved energy and performance (AGR, PV, FV, WAN, EB), pp. 755–760.
DATE-2007-MathaikuttySKLD #design #fault #generative #testing #validation: Design fault directed test generation for microprocessor validation (DM, SKS, SVK, DJL, AD), pp. 761–766.
DATE-2007-EckerESSVH #abstraction #interactive #performance #representation #simulation: Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance (WE, VE, LS, TS, MV, MH), pp. 767–772.
DATE-2007-MoserTBB #adaptation #energy #power management: Adaptive power management in energy harvesting systems (CM, LT, DB, LB), pp. 773–778.
DATE-2007-QiuTW #modelling #optimisation #power management #probability #robust: Stochastic modeling and optimization for robust power management in a partially observable system (QQ, YT, QW), pp. 779–784.
DATE-2007-HuangG #energy #optimisation #performance #realtime #scalability: Efficient and scalable compiler-directed energy optimization for realtime applications (PKH, SG), pp. 785–790.
DATE-2007-NiuQ #energy #interactive #realtime #scheduling: Interactive presentation: Peripheral-conscious scheduling on energy minimization for weakly hard real-time systems (LN, GQ), pp. 791–796.
DATE-2007-WatanabeKINN #constraints #energy #interactive #multi #performance #scheduling: Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC (RW, MK, MI, HN, TN), pp. 797–802.
DATE-2007-JanapsatyaIPH #agile #simulation: Instruction trace compression for rapid instruction cache simulation (AJ, AI, SP, JH), pp. 803–808.
DATE-2007-BonnyH #performance: Efficient code density through look-up table compression (TB, JH), pp. 809–814.
DATE-2007-FeiS #architecture #monitoring #set: Microarchitectural support for program code integrity monitoring in application-specific instruction set processors (YF, ZJS), pp. 815–820.
DATE-2007-SheldonVL #design #interactive #paradigm #using: Interactive presentation: Soft-core processor customization using the design of experiments paradigm (DS, FV, SL), pp. 821–826.
DATE-2007-X07a #power management: Power supply and power management in Ubicom, p. 827.
DATE-2007-BrandenburgSHEE #algorithm #approach #design #novel #prototype: From algorithm to first 3.5G call in record time: a novel system design approach based on virtual prototyping and its consequences for interdisciplinary system design teams (MB, AS, SH, JE, TE), pp. 828–830.
DATE-2007-PaganiniKDCC #challenge #design #multi: Portable multimedia SoC design: a global challenge (MP, GK, SD, GC, VC), pp. 831–834.
DATE-2007-Wingen #design #question #what: What if you could design tomorrow’s system today? (NW), pp. 835–840.
DATE-2007-HashempourL #detection #fault #modelling: Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs (HH, FL), pp. 841–846.
DATE-2007-JangKL #fault #profiling #reduction #self: Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profiling (BJ, YBK, FL), pp. 847–852.
DATE-2007-WielageMAW #design #embedded #performance: Design and DfT of a high-speed area-efficient embedded asynchronous FIFO (PW, EJM, MA, CW), pp. 853–858.
DATE-2007-DuboisMAWLW #analysis #embedded #quality: Test quality analysis and improvement for an embedded asynchronous FIFO (TD, EJM, MA, PW, EL, CW), pp. 859–864.
DATE-2007-RaoOK #fault tolerance #interactive #logic: Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs (WR, AO, RK), pp. 865–869.
DATE-2007-TangX #debugging #framework #manycore #platform: A multi-core debug platform for NoC-based systems (ST, QX), pp. 870–875.
DATE-2007-MossNFFBA #hardware #performance #simulation: Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support (LM, MdN, LF, SF, GB, EMA), pp. 876–881.
DATE-2007-BombieriFP #design #functional #incremental #refinement #validation: Incremental ABV for functional validation of TL-to-RTL design refinement (NB, FF, GP), pp. 882–887.
DATE-2007-MavroidisP #hardware #performance #synthesis: Efficient testbench code synthesis for a hardware emulator system (IM, IP), pp. 888–893.
DATE-2007-EckerESVH #framework #implementation #interactive #transaction: Interactive presentation: Implementation of a transaction level assertion framework in SystemC (WE, VE, TS, MV, MH), pp. 894–899.
DATE-2007-VermaHR #automation #behaviour #functional #generative #interactive #modelling: Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions (SV, IGH, KR), pp. 900–905.
DATE-2007-ChenSN #behaviour #composition #semantics #specification: Compositional specification of behavioral semantics (KC, JS, SN), pp. 906–911.
DATE-2007-HuangT #analysis #correlation #multi #performance #using: Performance analysis of multimedia applications using correlated streams (KH, LT), pp. 912–917.
DATE-2007-DerbekSWWPP #framework #platform #simulation: Simulation platform for UHF RFID (VD, CS, RW, DW, JPP, MP), pp. 918–923.
DATE-2007-BauerPT #analysis #hybrid #modelling: Tool-support for the analysis of hybrid systems and models (AB, MP, MT), pp. 924–929.
DATE-2007-FengWZKS #automation #black box #generative #interactive #realtime: Interactive presentation: Automatic model generation for black box real-time systems (THF, LW, WZ, SK, SAS), pp. 930–935.
DATE-2007-WittmannVWNKFM #question: Life begins at 65: unless you are mixed signal? (RW, MV, HJW, NN, JK, JEdF, CM), pp. 936–941.
DATE-2007-BolotinCGK: Routing table minimization for irregular mesh NoCs (EB, IC, RG, AK), pp. 942–947.
DATE-2007-BrandCGB #communication: Congestion-controlled best-effort communication for networks-on-chip (JWvdB, CC, KG, TB), pp. 948–953.
DATE-2007-HanssonCG #configuration management #multi #network: Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip (AH, MC, KG), pp. 954–959.
DATE-2007-GalivancheKR #testing: Testing in the year 2020 (RG, RK, AR), pp. 960–965.
DATE-2007-GailliardNSV #modelling #platform #transaction: Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM (GG, EN, MS, FV), pp. 966–971.
DATE-2007-Soderquist #architecture: Event driven data processing architecture (IS), pp. 972–976.
DATE-2007-FietheMDOZ #configuration management: Reconfigurable system-on-chip data processing units for space imaging instruments (BF, HM, CD, BO, GZ), pp. 977–982.
DATE-2007-RousseauMGMLDG #certification #configuration management #using: Enabling certification for dynamic partial reconfiguration using a minimal flow (BR, PM, DG, DM, JDL, FD, YG), pp. 983–988.
DATE-2007-FerrignoPSL #design #identification #process: Identification of process/design issues during 0.18 µm technology qualification for space application (JF, PP, KS, DL), pp. 989–993.
DATE-2007-ManetMTCMGLAGLB #configuration management #hardware #interactive #programmable: Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics (PM, DM, LT, MDC, OM, YG, JDL, DA, CG, RL, VLB), pp. 994–999.
DATE-2007-TiwaryP #analysis #named: WAVSTAN: waveform based variational static timing analysis (SKT, JRP), pp. 1000–1005.
DATE-2007-SrivastavaR #agile: Rapid and accurate latch characterization via direct Newton solution of setup/hold times (SS, JSR), pp. 1006–1011.
DATE-2007-LasbouyguesWAM #analysis: Temperature and voltage aware timing analysis: application to voltage drops (BL, RW, NA, PM), pp. 1012–1017.
DATE-2007-TadesseSLBG #analysis #modelling #satisfiability #using: Accurate timing analysis using SAT and pattern-dependent delay models (DT, DS, EL, RIB, JG), pp. 1018–1023.
DATE-2007-BondarevCW #analysis #component #design #embedded #named #performance #tool support: CARAT: a toolkit for design and performance analysis of component-based embedded systems (ERVB, MRVC, PHNdW), pp. 1024–1029.
DATE-2007-AlessioFQT #design #embedded #modelling #simulation: Modeling and simulation alternatives for the design of networked embedded systems (EA, FF, DQ, MT), pp. 1030–1035.
DATE-2007-MamagkakisSC #design #middleware #optimisation #protocol: Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns (SM, DS, FC), pp. 1036–1041.
DATE-2007-VillanuevaVMBRL #lightweight #middleware #network: Lightweight middleware for seamless HW-SW interoperability, with application to wireless sensor networks (FJV, DV, FM, JB, FR, JCL), pp. 1042–1047.
DATE-2007-FummiPPQ #design #embedded #interactive #middleware: Interactive presentation: A middleware-centric design flow for networked embedded systems (FF, GP, RP, DQ), pp. 1048–1053.
DATE-2007-NahapetianLABS #configuration management #energy #network: Dynamic reconfiguration in sensor networks with regenerative energy sources (AN, PL, AA, LB, MS), pp. 1054–1059.
DATE-2007-JungP #nondeterminism #power management: Dynamic power management under uncertain information (HJ, MP), pp. 1060–1065.
DATE-2007-RaghavanLJCVC #embedded #power management #symmetry: Very wide register: an asymmetric register file organization for low power embedded processors (PR, AL, MJ, FC, DV, HC), pp. 1066–1071.
DATE-2007-ChoudhuryRRM #interactive #memory management: Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory (MRC, KR, SR, KM), pp. 1072–1077.
DATE-2007-BabighianKV #data mining #interactive #mining #optimisation: Interactive presentation: PowerQuest: trace driven data mining for power optimization (PB, GK, MYV), pp. 1078–1083.
DATE-2007-BriereGBNMGO #assessment #framework #platform: System level assessment of an optical NoC in an MPSoC platform (MB, BG, YB, GN, FM, FG, IO), pp. 1084–1089.
DATE-2007-SheibanyradPG #architecture #comparison #implementation #multi #network: Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture (AS, IMP, AG), pp. 1090–1095.
DATE-2007-OgrasM #analysis #modelling #performance: Analytical router modeling for networks-on-chip performance analysis (ÜYO, RM), pp. 1096–1101.
DATE-2007-SauerGD #composition #framework #interactive #platform: Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform (CS, MG, SD), pp. 1102–1107.
DATE-2007-PardessusDA #embedded: The methodological and technological dimensions of technology transfer for embedded systems in aeronautics and space (TP, HD, RA), pp. 1108–1109.
DATE-2007-GrossschadlTRHM #constraints #energy #evaluation #implementation #memory management: Energy evaluation of software implementations of block ciphers under memory constraints (JG, ST, CR, MH, MM), pp. 1110–1115.
DATE-2007-AlamRMGCS #configuration management: An area optimized reconfigurable encryptor for AES-Rijndael (MA, SR, DM, SG, DRC, IS), pp. 1116–1121.
DATE-2007-NarayananKB #clustering #performance: Performance aware secure code partitioning (SHKN, MTK, RRB), pp. 1122–1127.
DATE-2007-AarajRRJ #analysis #energy #execution #framework #platform: Energy and execution time analysis of a software-based trusted platform module (NA, AR, SR, NKJ), pp. 1128–1133.
DATE-2007-HungIGS #fault: Utilization of SECDED for soft error and variation-induced defect tolerance in caches (LDH, HI, MG, SS), pp. 1134–1139.
DATE-2007-NarayanasamyCC #fault #predict: Transient fault prediction based on anomalies in processor events (SN, AKC, BC), pp. 1140–1145.
DATE-2007-MehraraASCBA #fault #low cost: Low-cost protection for SER upsets and silicon defects (MM, MA, SS, KC, VB, TMA), pp. 1146–1151.
DATE-2007-MutyamV #process: Working with process variation aware caches (MM, NV), pp. 1152–1157.
DATE-2007-SanchezSSR #automation #effectiveness #generative #interactive #source code: Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor (ES, MS, GS, MSR), pp. 1158–1163.
DATE-2007-ZhuSD #functional #interactive #pipes and filters #validation: Interactive presentation: Functional and timing validation of partially bypassed processor pipelines (QZ, AS, ND), pp. 1164–1169.
DATE-2007-MoonBP #approach #composition #equivalence: A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states (IHM, PB, CP), pp. 1170–1175.
DATE-2007-GrosseKD #bound #functional #model checking: Estimating functional coverage in bounded model checking (DG, UK, RD), pp. 1176–1181.
DATE-2007-SafarpourV #abstraction #automation #debugging #design #refinement: Abstraction and refinement techniques in automated design debugging (SS, AGV), pp. 1182–1187.
DATE-2007-BloemGJPPW #automation #case study #hardware #interactive #specification #synthesis: Interactive presentation: Automatic hardware synthesis from specifications: a case study (RB, SJG, BJ, NP, AP, MW), pp. 1188–1193.
DATE-2007-MoselhyHD #3d #performance: pFFT in FastMaxwell: a fast impedance extraction solver for 3D conductor structures over substrate (TM, XH, LD), pp. 1194–1199.
DATE-2007-HuMWD #performance: Optimization-based wideband basis functions for efficient interconnect extraction (XH, TM, JKW, LD), pp. 1200–1205.
DATE-2007-MondalRKRLVM #3d #robust: Thermally robust clocking schemes for 3D integrated circuits (MM, AJR, SK, TR, GML, NV, YM), pp. 1206–1211.
DATE-2007-LinLTL #design #library #standard: Double-via-driven standard cell library design (TYL, THL, HHT, RBL), pp. 1212–1217.
DATE-2007-XuRC #analysis #interactive #pipes and filters #power management: Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining (JX, AR, MHC), pp. 1218–1223.
DATE-2007-PozziP #future of #question: A future of customizable processors: are we there yet? (LP, PGP), pp. 1224–1225.
DATE-2007-SpindlerJ #estimation #performance: Fast and accurate routing demand estimation for efficient routability-driven placement (PS, FMJ), pp. 1226–1231.
DATE-2007-AzzoniBDFGV #optimisation: Yield-aware placement optimization (PA, MB, ND, FF, CG, WV), pp. 1232–1237.
DATE-2007-MogalB #architecture #reduction: Microarchitecture floorplanning for sub-threshold leakage reduction (HM, KB), pp. 1238–1243.
DATE-2007-OlivePF #industrial: Industrial applications (XO, JMP, DF), pp. 1244–1245.
DATE-2007-Botti #challenge #embedded #industrial: Flying embedded: the industrial scene and challenges for embedded systems in aeronautics and space (JB), p. 1246.
DATE-2007-AlhoHHH #design #hardware: Compact hardware design of Whirlpool hashing core (TA, PH, MH, TDH), pp. 1247–1252.
DATE-2007-PeterLP #encryption #flexibility #hardware #reduction: Flexible hardware reduction for elliptic curve cryptography in GF(2m) (SP, PL, KP), pp. 1259–1264.
DATE-2007-LinFYL #design #encryption #hardware: Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware (KJL, SCF, SHY, CCL), pp. 1265–1270.
DATE-2007-RosselloBBS #statistics #testing: Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs (JLR, CdB, SAB, JS), pp. 1271–1276.
DATE-2007-DasM #analysis: Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry (TD, PRM), pp. 1277–1282.
DATE-2007-HongSCY #adaptation: A two-tone test method for continuous-time adaptive equalizers (DH, SS, KTC, CPY), pp. 1283–1288.
DATE-2007-AitkenI #design #embedded #worst-case: Worst-case design and margin for embedded SRAM (RCA, SI), pp. 1289–1294.
DATE-2007-FavalliM #detection #fault #interactive: Interactive presentation: Pulse propagation for the detection of small delay defects (MF, CM), pp. 1295–1300.
DATE-2007-ZjajoAG #interactive #monitoring #parametricity #process: Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits (AZ, MJBA, JPdG), pp. 1301–1306.
DATE-2007-FangH #hybrid #performance #satisfiability: A new hybrid solution to boost SAT solver performance (LF, MSH), pp. 1307–1313.
DATE-2007-WuLLH #named #robust #satisfiability: QuteSAT: a robust circuit-based SAT solver for complex circuit structure (CAW, THL, CCL, CYH), pp. 1313–1318.
DATE-2007-CabodiNQ #induction #invariant #model checking: Boosting the role of inductive invariants in model checking (GC, SN, SQ), pp. 1319–1324.
DATE-2007-KroeningS #image #interactive #proving #refinement #using #word: Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs (DK, NS), pp. 1325–1330.
DATE-2007-BonziniP #automation #polynomial #set: Polynomial-time subgraph enumeration for automated instruction set extension (PB, LP), pp. 1331–1336.
DATE-2007-ReshadiG #architecture #embedded #low level #programming: Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems (MR, DG), pp. 1337–1342.
DATE-2007-GeWL #configuration management #embedded #memory management #named #power management: DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems (ZG, WFW, HBL), pp. 1343–1348.
DATE-2007-KraemerLAM #interactive #parallel #program transformation #source code #using: Interactive presentation: SoftSIMD — exploiting subword parallelism using source code transformations (SK, RL, GA, HM), pp. 1349–1354.
DATE-2007-MeijerKTK #interactive #network #process: Interactive presentation: A process splitting transformation for Kahn process networks (SM, BK, AT, EAdK), pp. 1355–1360.
DATE-2007-YangG: Computing synchronizer failure probabilities (SY, MRG), pp. 1361–1366.
DATE-2007-BaneresCK: Layout-aware gate duplication and buffer insertion (DB, JC, MK), pp. 1367–1372.
DATE-2007-NiM #self: Self-heating-aware optimal wire sizing under Elmore delay model (MN, SOM), pp. 1373–1378.
DATE-2007-SingheeR #monte carlo #novel #performance #simulation #statistics: Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application (AS, RAR), pp. 1379–1384.
DATE-2007-FengZTC #design #fault #metric #validation: Clock domain crossing fault model and coverage metric for validation of SoC design (YF, ZZ, DT, XC), pp. 1385–1390.
DATE-2007-ChenZLC #analysis #performance #statistics: Fast statistical circuit analysis with finite-point based transistor model (MC, WZ, FL, YC), pp. 1391–1396.
DATE-2007-SchneiderSKW #interactive #simulation #statistics: Interactive presentation: Statistical simulation of high-frequency bipolar circuits (WS, MS, WK, HW), pp. 1397–1402.
DATE-2007-RiffiodCPV #development: Development and industrialisation (MR, PC, CP, JLV), pp. 1403–1405.
DATE-2007-SchamannHLB #algorithm #architecture #case study #design #power management: Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system (MS, SH, UL, MB), pp. 1406–1411.
DATE-2007-GrassmannRS #architecture #multi #physics #standard: Mapping the physical layer of radio standards to multiprocessor architectures (CG, MR, MS), pp. 1412–1417.
DATE-2007-RenterghemDVVQ #compilation #development #using: Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow (KVR, PD, DV, JV, XZQ), pp. 1418–1423.
DATE-2007-CrepaldiCGZ #design #effectiveness #top-down: An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip (MC, MRC, MG, MZ), pp. 1424–1429.
DATE-2007-BarajasCCMGCBI #behaviour #interactive #modelling #optimisation: Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems (EB, RC, DC, DM, JLG, IC, SB, MI), pp. 1430–1435.
DATE-2007-Miskov-ZivanovM #analysis #fault: Soft error rate analysis for sequential circuits (NMZ, DM), pp. 1436–1441.
DATE-2007-SeshiaLM #fault: Verification-guided soft error resilience (SAS, WL, SM), pp. 1442–1447.
DATE-2007-RhodLC #architecture #performance: A low-SER efficient core processor architecture for future technologies (ELR, CALL, LC), pp. 1448–1453.
DATE-2007-ChoudhuryM #analysis #logic #reliability #scalability: Accurate and scalable reliability analysis of logic circuits (MRC, KM), pp. 1454–1459.
DATE-2007-GillPW #fault #interactive #power management #symmetry: Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA (BSG, CAP, FGW), pp. 1460–1465.
DATE-2007-Kahng #challenge #design: Design challenges at 65nm and beyond (ABK), pp. 1466–1467.
DATE-2007-Kopetz #architecture #embedded: The ARTEMIS cross-domain architecture for embedded systems (HK), pp. 1468–1469.
DATE-2007-Jerraya #architecture #implementation #modelling: HW/SW implementation from abstract architecture models (AAJ), pp. 1470–1471.
DATE-2007-HuynhM #embedded #realtime: Instruction-set customization for real-time embedded systems (HPH, TM), pp. 1472–1477.
DATE-2007-ParkPH #memory management #novel #stack: A novel technique to use scratch-pad memory for stack management (SP, HwP, SH), pp. 1478–1483.
DATE-2007-PuautP #comparison #realtime: Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison (IP, CP), pp. 1484–1489.
DATE-2007-SugiharaIM #architecture #multi #reliability #scheduling: Task scheduling for reliable cache architectures of multiprocessor systems (MS, TI, KM), pp. 1490–1495.
DATE-2007-Wong #equation #performance #symmetry #using: Fast positive-real balanced truncation of symmetric systems using cross Riccati equations (NW), pp. 1496–1501.
DATE-2007-ZhuP #algorithm #graph #probability #random: Random sampling of moment graph: a stochastic Krylov-reduction algorithm (ZZ, JRP), pp. 1502–1507.
DATE-2007-FanMTCH #correlation #order #reduction #statistics: Statistical model order reduction for interconnect circuits considering spatial correlations (JF, NM, SXDT, YC, XH), pp. 1508–1513.
DATE-2007-ZhuZCXZ #grid #probability #process: A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology (HZ, XZ, WC, JX, DZ), pp. 1514–1519.
DATE-2007-BronckersSPVR #analysis #interactive #simulation #verification: Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO’s (SB, CS, GVdP, GV, YR), pp. 1520–1525.
DATE-2007-LiuDSY #estimation #power management: Accurate temperature-dependent integrated circuit leakage power estimation is easy (YL, RPD, LS, HY), pp. 1526–1531.
DATE-2007-GhoshBR #adaptation #scheduling #synthesis #using: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling (SG, SB, KR), pp. 1532–1537.
DATE-2007-MangassarianVSNA #estimation #process #pseudo #satisfiability #using: Maximum circuit activity estimation using pseudo-boolean satisfiability (HM, AGV, SS, FNN, MSA), pp. 1538–1543.
DATE-2007-SathanurCBMMP #bound #clustering #interactive #performance: Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing (AVS, AC, LB, AM, EM, MP), pp. 1544–1549.
DATE-2007-HwangCR #interactive #process #scalability: Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling (MEH, TC, KR), pp. 1550–1555.
DATE-2007-AycinenaBLMGW #open source #question #towards: Towards total open source in aeronautics and space? (PA, EB, GL, RM, FG, AW), p. 1556.
DATE-2007-GburzynskiKO #ad hoc #low cost #network #performance #protocol: A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks (PG, BK, WO), pp. 1557–1562.
DATE-2007-KrishnaiahES #architecture #configuration management #scalability: Scalable reconfigurable channel decoder architecture for future wireless handsets (GK, NE, SS), pp. 1563–1568.
DATE-2007-KhanATE #algorithm #implementation #pipes and filters #sorting: A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems (ZK, TA, JST, ATE), pp. 1569–1574.
DATE-2007-TychopoulosK #architecture #communication #optimisation: Optimization of the “FOCUS” Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channels (AT, OGK), pp. 1575–1580.
DATE-2007-PanC #analysis #component #fault #framework #quality #reliability: A framework for system reliability analysis considering both system error tolerance and component test quality (SJ(RP, KTC), pp. 1581–1586.
DATE-2007-LeveugleAMTMMFRT #evaluation #fault #modelling: Experimental evaluation of protections against laser-induced faults and consequences on fault modeling (RL, AA, VM, ET, PM, CM, NF, JBR, AT), pp. 1587–1592.
DATE-2007-GodardDTS #design #embedded #evaluation #reliability: Evaluation of design for reliability techniques in embedded flash memories (BG, JMD, LT, GS), pp. 1593–1598.
DATE-2007-HsiehLB #detection #fault #reduction: Reduction of detected acceptable faults for yield improvement via error-tolerance (TYH, KJL, MAB), pp. 1599–1604.
DATE-2007-NardiTNAGLS #analysis #design #statistics #using: Use of statistical timing analysis on real designs (AN, ET, SN, AA, SG, TL, JS), pp. 1605–1610.
DATE-2007-0004XJ #analysis #novel #statistics: A novel criticality computation method in statistical timing analysis (FW, YX, HJ), pp. 1611–1616.
DATE-2007-SilvaSP #performance: Efficient computation of the worst-delay corner (LGeS, LMS, JRP), pp. 1617–1622.
DATE-2007-JuCR #analysis #scheduling: Accounting for cache-related preemption delay in dynamic priority schedulability analysis (LJ, SC, AR), pp. 1623–1628.
DATE-2007-ChenKYK #energy #realtime #scheduling: Energy-efficient real-time task scheduling with task rejection (JJC, TWK, CLY, KJK), pp. 1629–1634.
DATE-2007-CucuG #multi #scheduling: Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems (LC, JG), pp. 1635–1640.
DATE-2007-QiuXSS #embedded #energy #multi #realtime: Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems (MQ, CX, ZS, EHMS), pp. 1641–1646.
DATE-2007-EjlaliARM #energy #fault tolerance #network #performance: Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks (AE, BMAH, PMR, SGM), pp. 1647–1652.
DATE-2007-HumenayTS #manycore #performance #process #symmetry: Impact of process variations on multicore performance symmetry (EH, DT, KS), pp. 1653–1658.
DATE-2007-CoskunRW #scheduling: Temperature aware task scheduling in MPSoCs (AKC, TSR, KW), pp. 1659–1664.
DATE-2007-GolubevaLPM #architecture: Architectural leakage-aware management of partitioned scratchpad memories (OG, ML, MP, EM), pp. 1665–1670.
DATE-2007-KandemirYSO #memory management #scheduling: Memory bank aware dynamic loop scheduling (MTK, TY, SWS, ÖÖ), pp. 1671–1676.
DATE-2007-ButtSRPS #optimisation #synthesis: System level clock tree synthesis for power optimization (SAB, SS, JR, AP, ES), pp. 1677–1682.

Rudy Lauwereins, Jan MadsenProceedings of the 11th Conference on Design, Automation and Test in EuropeDATE, 2007.

Contents (292 items)

Rudy Lauwereins, Jan Madsen
Proceedings of the 11th Conference on Design, Automation and Test in Europe
DATE, 2007.