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Travelled to:
1 × USA
Collaborated with:
M.Tomita T.Yamamoto F.Sumikawa
Talks about:
multipl (2) circuit (1) rectif (1) output (1) design (1) logic (1) error (1)

Person: Kotaro Hirano

DBLP DBLP: Hirano:Kotaro

Contributed to:

DAC 19941994

Wrote 1 papers:

DAC-1994-TomitaYSH #design #fault #logic #multi
Rectification of Multiple Logic Design Errors in Multiple Output Circuits (MT, TY, FS, KH), pp. 212–217.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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