BibSLEIGH — Proceedings of the 31st Design Automation Conference

Michael J. Lorenzetti
Proceedings of the 31st Design Automation Conference
DAC, 1994.

SYS

@proceedings{DAC-1994,
	acmid         = "196244",
	address       = "San Diego, California, USA",
	editor        = "Michael J. Lorenzetti",
	isbn          = "0-7803-1836-6",
	publisher     = "{ACM Press}",
	title         = "{Proceedings of the 31st Design Automation Conference}",
	year          = 1994,
}

Contents (126 items)

DAC-1994-ChouB #realtime #scheduling: Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems (PHC, GB), pp. 1–4.
DAC-1994-HuangD #pipes and filters #set #synthesis: Synthesis of Instruction Sets for Pipelined Microprocessors (IJH, AMD), pp. 5–11.
DAC-1994-MonteiroDL #estimation #logic #performance #process: A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits (JCM, SD, BL), pp. 12–17.
DAC-1994-TsuiPD #approximate: Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs (CYT, MP, AMD), pp. 18–23.
DAC-1994-OchottaRC #agile #named #synthesis #tool support: ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits (ESO, RAR, LRC), pp. 24–30.
DAC-1994-CharbonMPS #optimisation: Simultaneous Placement and Module Optimization of Analog IC’s (EC, EM, DP, ALSV), pp. 31–35.
DAC-1994-MehrotraFL #approach #optimisation #probability: Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits (SM, PDF, WL), pp. 36–40.
DAC-1994-Prabhu: Management Issues in Eda (AMP), pp. 41–47.
DAC-1994-JongL #communication #concurrent #design #petri net: A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules (GGdJ, BL), pp. 49–55.
DAC-1994-KondratyevKLVY #implementation #independence: Basic Gate Implementation of Speed-Independent Circuits (AK, MK, BL, PV, AY), pp. 56–62.
DAC-1994-PuriG #approach #clustering #composition #synthesis: A Modular Partitioning Approach for Asynchronous Circuit Synthesis (RP, JG), pp. 63–69.
DAC-1994-NielsenK #analysis #performance #simulation: Performance Analysis Based on Timing Simulation (CDN, MK), pp. 70–76.
DAC-1994-AsharM #low cost #set: Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications (PA, SM), pp. 77–80.
DAC-1994-ChakradharBA #algorithm: An Exact Algorithm for Selecting Partial Scan Flip-Flops (STC, AB, VDA), pp. 81–86.
DAC-1994-ChakradharD: Resynthesis and Retiming for Optimum Partial Scan (STC, SD), pp. 87–93.
DAC-1994-FangG #low cost #testing: Clock Grouping: A Low Cost DFT Methodology for Delay Testing (WCF, SKG), pp. 94–99.
DAC-1994-LamBS #finite #state machine: Exact Minimum Cycle Times for Finite State Machines (WKCL, RKB, ALSV), pp. 100–105.
DAC-1994-WalkupB #interface #synthesis #verification: Interface Timing Verification with Application to Synthesis (EAW, GB), pp. 106–112.
DAC-1994-GuptaS #automation #design #multi #verification: Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs (APG, DPS), pp. 113–119.
DAC-1994-DagaB #composition #interface #state machine: The Minimization and Decomposition of Interface State Machines (AJD, WPB), pp. 120–125.
DAC-1994-JyuM #design #logic #modelling #statistics #synthesis: Statistical Delay Modeling in Logic Design and Synthesis (HFJ, SM), pp. 126–130.
DAC-1994-Murphy #standard: Partnering with EDA Vendors: Tips, Techniques, and the Role of Standards (SM), pp. 131–134.
DAC-1994-Maly #design #perspective: Cost of Silicon Viewed from VLSI Design Perspective (WM), pp. 135–142.
DAC-1994-VerbauwhedeSR #estimation #memory management #synthesis: Memory Estimation for High Level Synthesis (IV, CJS, JMR), pp. 143–148.
DAC-1994-KolsonND #memory management #synthesis: Minimization of Memory Traffic in High-Level Synthesis (DJK, AN, NDD), pp. 149–154.
DAC-1994-AloqeelyC #algorithm #synthesis: Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms (MA, CYRC), pp. 155–160.
DAC-1994-Fernandez #industrial: Intellectual Property Protection in the EDA Industry (DSF), pp. 161–163.
DAC-1994-ZhuW #bound: Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs (KZ, DFW), pp. 165–170.
DAC-1994-SunL #2d #architecture: Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture (YS, CLL), pp. 171–176.
DAC-1994-HaradaK #optimisation #performance: A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI’s (IH, HK), pp. 177–181.
DAC-1994-MadhwapathySBP #approach #multi: A Unified Approach to Multilayer Over-the-Cell Routing (SM, NAS, SB, AP), pp. 182–187.
DAC-1994-PotkonjakSC #constant #multi #performance #using: Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise Matching (MP, MBS, AC), pp. 189–194.
DAC-1994-BhattacharyaDB #optimisation #resource management: Clock Period Optimization During Resource Sharing and Assignment (SB, SD, FB), pp. 195–200.
DAC-1994-PotkonjakD #optimisation #resource management #testing #using: Optimizing Resource Utilization and Testability Using Hot Potato Techniques (MP, SD), pp. 201–205.
DAC-1994-HarrisO #architecture #concurrent #design #synthesis: Microarchitectural Synthesis of VLSI Designs with High Test Concurrency (IGH, AO), pp. 206–211.
DAC-1994-TomitaYSH #design #fault #logic #multi: Rectification of Multiple Logic Design Errors in Multiple Output Circuits (MT, TY, FS, KH), pp. 212–217.
DAC-1994-KuehlmannCSL #fault #verification: Error Diagnosis for Transistor-Level Verification (AK, DIC, AS, DPL), pp. 218–224.
DAC-1994-ShipleHSB #heuristic #using: Heuristic Minimization of BDDs Using Don’t Cares (TRS, RH, ALSV, RKB), pp. 225–231.
DAC-1994-ZhuW94a: Clock Skew Minimization During FPGA Placement (KZ, DFW), pp. 232–237.
DAC-1994-KuznarBZ #clustering #multi: Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect (RK, FB, BZ), pp. 238–243.
DAC-1994-ChouLCDL #clustering #logic: Circuit Partitioning for Huge Logic Emulation Systems (NCC, LTL, CKC, WJD, RL), pp. 244–249.
DAC-1994-GuptaCDP #design #experience #image #tool support #using: Experience with Image Compression Chip Design using Unified System Construction Tools (PG, CTC, JCDB, ACP), pp. 250–256.
DAC-1994-KeeSGK #framework #using: The Use of CAD Frameworks in a CIM Environment (WTK, DS, JG, LKK), pp. 257–261.
DAC-1994-TeraiGNSO #automation #concept #design #performance: Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 (HT, KG, YN, YS, YO), pp. 262–269.
DAC-1994-HachtelMPS #analysis #finite #probability #scalability #state machine: Probabilistic Analysis of Large Finite State Machines (GDH, EM, AP, FS), pp. 270–275.
DAC-1994-HuYD #performance #verification: New Techniques for Efficient Verification with Implicitly Conjoined BDDs (AJH, GY, DLD), pp. 276–282.
DAC-1994-AzizTB #finite #state machine: BDD Variable Ordering for Interacting Finite State Machines (AA, ST, RKB), pp. 283–288.
DAC-1994-CabodiCQ #traversal: Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths (GC, PC, SQ), pp. 289–293.
DAC-1994-LanZG #multi #programmable: Placement and Routing for a Field Programmable Multi-Chip Module (SL, AZ, AEG), pp. 295–300.
DAC-1994-NagR: Performance-Driven Simultaneous Place and Route for Row-Based FPGAs (SN, RAR), pp. 301–307.
DAC-1994-ChangCWM #layout #logic #synthesis: Layout Driven Logic Synthesis for FPGAs (SCC, KTC, NSW, MMS), pp. 308–313.
DAC-1994-McMillan #design #formal method: Fitting Formal Methods into the Design Cycle (KLM), pp. 314–319.
DAC-1994-SarabiSCP #2d #approach #array #design #logic #physics #synthesis: A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays (AS, NS, MCJ, MAP), pp. 321–326.
DAC-1994-KannanSF #algorithm #optimisation: A Methodology and Algorithms for Post-Placement Delay Optimization (LNK, PS, HGF), pp. 327–332.
DAC-1994-ImanPC #fuzzy #logic #using: Technology Mapping Using Fuzzy Logic (SI, MP, KC), pp. 333–338.
DAC-1994-TsaiM #using: Boolean Matching Using Generalized Reed-Muller Forms (CCT, MMS), pp. 339–344.
DAC-1994-ParulkarBN #representation: Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST (IP, MAB, CN), pp. 345–356.
DAC-1994-ChakrabartyH #named #testing: DFBT: A Design-for-Testability Method Based on Balance Testing (KC, JPH), pp. 351–357.
DAC-1994-PomeranzR #combinator #fault #scalability #using: Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points (IP, SMR), pp. 358–364.
DAC-1994-ChengC #fault #generative #quality #testing: Generation of High Quality Non-Robust Tests for Path Delay Faults (KTC, HCC), pp. 365–369.
DAC-1994-ShyurCP #on the #pipes and filters #testing: On Testing Wave Pipelined Circuits (JCS, HPC, TMP), pp. 370–374.
DAC-1994-Edahiro #algorithm #performance: An Efficient Zero-Skew Routing Algorithm (ME), pp. 375–380.
DAC-1994-BoeseKMR: Rectilinear Steiner Trees with Minimum Elmore Delay (KDB, ABK, BAM, GR), pp. 381–386.
DAC-1994-Sapatnekar #optimisation: RC Interconnect Optimization Under the Elmore Delay Model (SSS), pp. 387–391.
DAC-1994-VittalM #design #using: Minimal Delay Interconnect Design Using Alphabetic Trees (AV, MMS), pp. 392–396.
DAC-1994-YuBS #3d #algorithm #aspect-oriented: Algorithmic Aspects of Three Dimensional MCM Routing (QY, SB, NAS), pp. 397–401.
DAC-1994-XueHJ: Routing for Manufacturability (HX, EPH, JAGJ), pp. 402–406.
DAC-1994-MurgaiBS #composition #encoding #functional #using: Optimum Functional Decomposition Using Encoding (RM, RKB, ALSV), pp. 408–414.
DAC-1994-DrechslerSTBP #diagrams #functional #order #performance #representation: Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams (RD, AS, MT, BB, MAP), pp. 415–419.
DAC-1994-Minato #algebra #set #using: Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs (SiM), pp. 420–424.
DAC-1994-SaldanhaHMBS #optimisation #performance #using: Performance Optimization Using Exact Sensitization (AS, HH, PCM, RKB, ALSV), pp. 425–429.
DAC-1994-IwamaH #generative #logic #random: Random Generation of Test Instances for Logic Optimizers (KI, KH), pp. 430–434.
DAC-1994-Keutzer #co-evolution #design: Hardware-Software Co-Design and ESDA (KK), pp. 435–436.
DAC-1994-KalavadeeL #co-evolution #design #hardware: Manifestations of Heterogeneity in Hardware/Software Co-Design (AK, EAL), pp. 437–438.
DAC-1994-Rowson #hardware: Hardware/Software Co-Simulation (JAR), pp. 439–440.
DAC-1994-PrasadAB #design #incremental #synthesis: A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes (SCP, PA, PWB), pp. 441–446.
DAC-1994-LeviaMR #analysis #design: Lessons in Language Design: Cost/Benefit analysis of VHDL Features (OL, SM, JR), pp. 447–453.
DAC-1994-AzizBCHKKRSSTWBS #named #verification: HSIS: A BDD-Based Environment for Formal Verification (AA, FB, STC, RH, TK, SCK, RKR, TRS, VS, ST, HYW, RKB, ALSV), pp. 454–459.
DAC-1994-KellyPC #agile #prototype: Rapid Prototyping of ASIC Based Systems (PHK, KJP, PMC), pp. 460–465.
DAC-1994-KissionDJ #design: Structured Design Methodology for High-Level Design (PK, HD, AAJ), pp. 466–471.
DAC-1994-BaldwinC #design #graph grammar #using: Design Methodology Management Using Graph Grammars (RAB, MJC), pp. 472–478.
DAC-1994-RadivojevicB #execution #scheduling: Incorporating Speculative Execution in Exact Control-Dependent Scheduling (IPR, FB), pp. 479–484.
DAC-1994-PassosSB #multi #pipes and filters #scheduling: Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation (NLP, EHMS, SCB), pp. 485–490.
DAC-1994-BhattacharyaDB94a #analysis #optimisation #performance #specification: Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications (SB, SD, FB), pp. 491–496.
DAC-1994-BenedettoLSY #problem: Chain Closure: A Problem in Molecular CAD (MDDB, PL, ALSV, KY), pp. 497–502.
DAC-1994-PomeranzR94a #fault #on the: On Improving Fault Diagnosis for Synchronous Sequential Circuits (IP, SMR), pp. 504–509.
DAC-1994-NagumoNNMM #fault #named #reduction #using: VFSIM: Vectorized Fault Simulator Using a Reduction Technique Excluding Temporarily Unobservable Faults (TN, MN, TN, MM, SM), pp. 510–515.
DAC-1994-HeraguBA #fault #performance: An Efficient Path Delay Fault Coverage Estimator (KH, MLB, VDA), pp. 516–521.
DAC-1994-HenftlingWA #fault #simulation: Path Hashing to Accelerate Delay Fault Simulation (MH, HCW, KA), pp. 522–526.
DAC-1994-Radtke #design #hardware #process #scalability: The AT&T 5ESS Hardware Design Environment: A Large System’s Hardware design Process (KAR), pp. 527–531.
DAC-1994-Casavant #design #named #pipes and filters #programmable: MIST — A Design Aid for Programmable Pipelined Processors (AEC), pp. 532–536.
DAC-1994-JunH #automation #pipes and filters #synthesis: Automatic Synthesis of Pipeline Structures with Variable Data Initiation Intervals (HSJ, SYH), pp. 537–541.
DAC-1994-FannRJ #scheduling #synthesis: Global Scheduling for High-Level Synthesis Applications (YF, MR, RJ), pp. 542–546.
DAC-1994-NarayanG #communication #generative #protocol: Protocol Generation for Communication Channels (SN, DG), pp. 547–551.
DAC-1994-KarriO #architecture #detection #fault #self #synthesis: Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis (RK, AO), pp. 552–556.
DAC-1994-ArnsteinT #abstraction #behaviour #synthesis #tool support: The Attributed-Behavior Abstraction and Synthesis Tools (LFA, DET), pp. 557–561.
DAC-1994-KahngM #analysis #equation #using: Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model (ABK, SM), pp. 563–569.
DAC-1994-KovalFSD #named: MONSTR: A Complete Thermal Simulator of Electronic Systems (VK, IWF, AJS, SWD), pp. 570–575.
DAC-1994-DartuMQP #performance: A Gate-Delay Model for high-Speed CMOS Circuits (FD, NM, JQ, LTP), pp. 576–580.
DAC-1994-ChenF #analysis #using: Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation (CJC, WSF), pp. 581–585.
DAC-1994-Fox #design: The Design of High-Performance Microprocessors at Digital (TFF), pp. 586–591.
DAC-1994-Nishimukai: Hitachi-PA/50, SH Series Microcontroller (TN), pp. 592–593.
DAC-1994-SchobingerN #design #power management: Low Power CMOS Design Strategies (MS, TGN), pp. 594–595.
DAC-1994-BeattyB #simulation #using #verification: Formally Verifying a Microprocessor Using a Simulation Methodology (DLB, REB), pp. 596–602.
DAC-1994-BhagwatiD #automation #pipes and filters #verification: Automatic Verification of Pipelined Microprocessors (VB, SD), pp. 603–608.
DAC-1994-VerlindKJLM #abstraction #communication #performance #verification: A Time Abstraction Method for Efficient Verification of Communicating Systems (EV, TK, GGdJ, BL, HDM), pp. 609–614.
DAC-1994-KrishnakumarC #hybrid #modelling #on the #set: On the Computation of the Set of Reachable States of Hybrid Models (ASK, KTC), pp. 615–621.
DAC-1994-Nguyen #performance #simulation: Efficient Simulation of Lossy and Dispersive Transmission Lines (TVN), pp. 622–627.
DAC-1994-HaqueEC #megamodelling #multi #simulation: A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line Interconnections (MH, AEZ, SC), pp. 628–633.
DAC-1994-SilveiraEWCK #approach #performance #simulation #using: An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data (LMS, IME, JW, MC, KSK), pp. 634–639.
DAC-1994-GuptaP #named #termination: OTTER: Optimal Termination of Transmission Lines Excluding Radiation (RG, LTP), pp. 640–645.
DAC-1994-RiessDJ #clustering #scalability #using: Partitioning Very Large Circuits Using Analytical Placement Techniques (BMR, KD, FMJ), pp. 646–651.
DAC-1994-AlpertK #clustering #multi #programming: Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming (CJA, ABK), pp. 652–657.
DAC-1994-LiuSC #clustering #data flow #latency: Data Flow Partitioning for Clock Period and Latency Minimization (LTL, MS, CKC), pp. 658–663.
DAC-1994-BuiM #algorithm #clustering #hybrid #performance #problem #search-based: A Fast and Stable Hybrid Genetic Algorithm for the Ratio-Cut Partitioning Problem on Hypergraphs (TNB, BRM), pp. 664–669.
DAC-1994-CongLB #clustering #multi #network: Acyclic Multi-Way Partitioning of Boolean Networks (JC, ZL, RB), pp. 670–675.
DAC-1994-WangB #automaton #network: Permissible Observability Relations in FSM Networks (HYW, RKB), pp. 677–683.
DAC-1994-KamVBS #algorithm: A Fully Implicit Algorithm for Exact State Minimization (TK, TV, RKB, ALSV), pp. 684–690.
DAC-1994-KrishnamoorthyM: Boolean Matching of Sequential Elements (SK, FM), pp. 691–697.
DAC-1994-RudnickPGN #algorithm #framework #generative #search-based #testing: Sequential Circuit Test Generation in a Genetic Algorithm Framework (EMR, JHP, GSG, TMN), pp. 698–704.
DAC-1994-SilvaS: Dynamic Search-Space Pruning Techniques in Path Sensitization (JPMS, KAS), pp. 705–711.
DAC-1994-VinnakotaA #fault #functional #generative #testing: Functional Test Generation for FSMs by Fault Extraction (BV, JA), pp. 712–715.
DAC-1994-ParkesBP #approach #generative #named #object-oriented #parallel #testing: ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation (SP, PB, JHP), pp. 717–721.
DAC-1994-DahlgrenL #modelling #network: Modeling of Intermediate Node States in switch-Level Networks (PD, PL), pp. 722–727.
DAC-1994-XakellisN #estimation #process #statistics: Statistical Estimation of the Switching Activity in Digital Circuits (MGX, FNN), pp. 728–733.
DAC-1994-Kapoor #metric #process: Improving the Accuracy of Circuit Activity Measurement (BK), pp. 734–739.

Michael J. LorenzettiProceedings of the 31st Design Automation ConferenceDAC, 1994.

Contents (126 items)

Michael J. Lorenzetti
Proceedings of the 31st Design Automation Conference
DAC, 1994.