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Travelled to:
1 × France
Collaborated with:
D.Kim M.J.Ciesielski S.Yang
Talks about:
simul (2) level (2) parallel (1) tempor (1) higher (1) model (1) gate (1) fast (1) use (1) hdl (1)

Person: Kyuho Shim

DBLP DBLP: Shim:Kyuho

Contributed to:

DATE 20112011

Wrote 1 papers:

DATE-2011-KimCSY #modelling #parallel #performance #simulation #using
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models (DK, MJC, KS, SY), pp. 1584–1589.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.