Proceedings of the 15th Conference on Design, Automation and Test in Europe
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Proceedings of the 15th Conference on Design, Automation and Test in Europe
DATE, 2011.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DATE-2011,
	address       = "Grenoble, France",
	isbn          = "978-1-61284-208-0",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 15th Conference on Design, Automation and Test in Europe}",
	year          = 2011,
}

Contents (318 items)

DATE-2011-Furber #architecture
Biologically-inspired massively-parallel architectures — Computing beyond a million processors (SBF), p. 1.
DATE-2011-KozhikkottuVRD #analysis #named #performance #variability
VESPA: Variability emulation for System-on-Chip performance analysis (VJK, RV, AR, SD), pp. 2–7.
DATE-2011-LungHKC #3d #manycore #online #optimisation #throughput
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization (CLL, YLH, DMK, SCC), pp. 8–13.
DATE-2011-WangLQS #memory management #reuse
An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems (YW, DL, ZQ, ZS), pp. 14–19.
DATE-2011-LiuOXL #energy #reduction
Register allocation for simultaneous reduction of energy and peak temperature on registers (TL, AO, CJX, ML), pp. 20–25.
DATE-2011-GobbatoCG #megamodelling #parallel #scalability
A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodels (LG, AC, SGT), pp. 26–31.
DATE-2011-BiKVSM #analysis #performance #statistics
Fast statistical analysis of RC nets subject to manufacturing variabilities (YB, KJvdK, JFV, LMS, NvdM), pp. 31–37.
DATE-2011-BoghratiS #analysis #grid #performance #power management #random
A scaled random walk solver for fast power grid analysis (BB, SSS), pp. 38–43.
DATE-2011-ZhangHCW #grid #network #power management #reduction
A block-diagonal structured model reduction scheme for power grid networks (ZZ, XH, CKC, NW), pp. 44–49.
DATE-2011-Micheli #design #logic #physics #question #synthesis
Logic synthesis and physical design: Quo vadis? (GDM), p. 50.
DATE-2011-PalframanKL #detection #fault #low cost
Time redundant parity for low-cost transient error detection (DJP, NSK, MHL), pp. 52–57.
DATE-2011-HuangHL #fault
Cross-layer optimized placement and routing for FPGA soft error mitigation (KH, YH, XL), pp. 58–63.
DATE-2011-YuH #fault #logic
Trigonometric method to handle realistic error probabilities in logic circuits (CCY, JPH), pp. 64–69.
DATE-2011-FazeliAMAT #estimation #fault #multi
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs) (MF, SNA, SGM, HA, MBT), pp. 70–75.
DATE-2011-LukasiewyczCM #concept #network #scheduling
FlexRay switch scheduling — A networking concept for electric vehicles (ML, SC, PM), pp. 76–81.
DATE-2011-KlobedanzK0 #approach #configuration management #fault tolerance #network
A reconfiguration approach for fault-tolerant FlexRay networks (KK, AK, WM), pp. 82–87.
DATE-2011-BaiDDC #network #program transformation #programming #runtime
Simplified programming of faulty sensor networks via code transformation and run-time interval computation (LSB, RPD, PAD, PHC), pp. 88–93.
DATE-2011-ChrysanthouCSP #algorithm #parallel
Parallel accelerators for GlimmerHMM bioinformatics algorithm (NC, GC, ES, IP), pp. 94–99.
DATE-2011-PaternaACPDB #algorithm #energy #manycore #online #performance #platform
An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms (FP, AA, AC, FP, GD, LB), pp. 100–105.
DATE-2011-MistryAFH #power management
Sub-clock power-gating technique for minimising leakage power during active mode (JNM, BMAH, DF, SH), pp. 106–111.
DATE-2011-KernST #automation #concept #data type #embedded #migration
An automated data structure migration concept — From CAN to Ethernet/IP in automotive embedded systems (CANoverIP) (AK, TS, JT), pp. 112–117.
DATE-2011-SieglHGB #embedded #modelling #specification #testing
Formal specification and systematic model-driven testing of embedded automotive systems (SS, KSJH, RG, CB), pp. 118–123.
DATE-2011-KapoorJ #design #embedded #power management #tutorial #verification
Embedded tutorial: Addressing critical power management verification issues in low power designs (BK, KMJ), p. 124.
DATE-2011-ChakrabortyR #manycore
Topologically homogeneous power-performance heterogeneous multicore systems (KC, SR), pp. 125–130.
DATE-2011-WannerBZAGS #embedded #scheduling #variability
Variability-aware duty cycle scheduling in long running embedded sensing systems (LFW, RB, SZ, CA, PG, MBS), pp. 131–136.
DATE-2011-HanumaiahV #manycore #realtime
Reliability-aware thermal management for hard real-time applications on multi-core processors (VH, SBKV), pp. 137–142.
DATE-2011-HanJS #analysis
Clause simplification through dominator analysis (HH, HJ, FS), pp. 143–148.
DATE-2011-ReimerPSB #integration #orthogonal
Integration of orthogonal QBF solving techniques (SR, FP, CS, BB), pp. 149–154.
DATE-2011-PavlenkoWSKDSG #algebra #named #problem #reasoning #smt #verification
STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra (EP, MW, DS, WK, AD, FS, GMG), pp. 155–160.
DATE-2011-GuoCSCWH #debugging #design #empirical #predict #verification
Empirical design bugs prediction for verification (QG, TC, HS, YC, YW, WH), pp. 161–166.
DATE-2011-ChenM #composition #functional #generative #testing
Decision ordering based property decomposition for functional test generation (MC, PM), pp. 167–172.
DATE-2011-LiuSTV #design #generative #towards #using #validation
Towards coverage closure: Using GoldMine assertions for generating design validation stimulus (LL, DS, WT, SV), pp. 173–178.
DATE-2011-BehrendLHRKR #embedded #hybrid #scalability #verification
Scalable hybrid verification for embedded software (JB, DL, PH, JR, TK, WR), pp. 179–184.
DATE-2011-ChenO #analysis #fault #image #statistics
Diagnosing scan chain timing faults through statistical feature analysis of scan images (MC, AO), pp. 185–190.
DATE-2011-BangaRH #testing
Design-for-test methodology for non-scan at-speed testing (MB, NPR, MSH), pp. 191–196.
DATE-2011-YangSSL #reduction #testing
A clock-gating based capture power droop reduction methodology for at-speed scan testing (BY, AS, SS, CL), pp. 197–203.
DATE-2011-AndalamRG #analysis #source code
Pruning infeasible paths for tight WCRT analysis of synchronous programs (SA, PSR, AG), pp. 204–209.
DATE-2011-StattelmannBR #analysis #manycore #performance #simulation
Fast and accurate resource conflict simulation for performance analysis of multi-core systems (SS, OB, WR), pp. 210–215.
DATE-2011-WangLH #approach #embedded
An approach to improve accuracy of source-level TLMs of embedded software (ZW, KL, AH), pp. 216–221.
DATE-2011-RazaghiG #development #embedded #manycore #realtime
Host-compiled multicore RTOS simulator for embedded real-time software development (PR, AG), pp. 222–227.
DATE-2011-MurugappaABJ #architecture #flexibility #multi #throughput
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding (PM, RAK, AB, MJ), pp. 228–233.
DATE-2011-BernardC #power management
A low-power VLIW processor for 3GPP-LTE complex numbers processing (CB, FC), pp. 234–239.
DATE-2011-HeidmannWP #architecture #detection #throughput
Architecture and FPGA-implementation of a high throughput K+-Best detector (NH, TW, SP), pp. 240–245.
DATE-2011-MadaniTCCD #detection #energy #standard
An energy-efficient 64-QAM MIMO detector for emerging wireless standards (NMM, TT, JC, PC, WRD), pp. 246–251.
DATE-2011-PangrleBCDJ #design #power management #verification
Beyond UPF & CPF: Low-power design and verification (BMP, JB, CC, OD, KMJ), p. 252.
DATE-2011-KhatibA #design #streaming
Buffering implications for the design space of streaming MEMS storage (MGK, LA), pp. 253–256.
DATE-2011-GoyalN #grid #performance #power management #using #verification
Efficient RC power grid verification using node elimination (AG, FNN), pp. 257–260.
DATE-2011-HealyL #3d #network #novel
A novel TSV topology for many-tier 3D power-delivery networks (MBH, SKL), pp. 261–264.
DATE-2011-HaronH #fault tolerance #hybrid #low cost
Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories (NZH, SH), pp. 265–268.
DATE-2011-ZiermannTS #adaptation #algorithm #named
DynOAA — Dynamic offset adaptation algorithm for improving response times of CAN systems (TZ, JT, ZS), pp. 269–272.
DATE-2011-SabatelliSFR #algorithm #estimation #metric
A sensor fusion algorithm for an integrated angular position estimation with inertial measurement units (SS, FS, LF, AR), pp. 273–276.
DATE-2011-MichelFP #embedded #simulation
Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation (LM, NF, FP), pp. 277–280.
DATE-2011-Niu #embedded #energy #realtime #scheduling
System-level energy-efficient scheduling for hard real-time embedded systems (LN), pp. 281–284.
DATE-2011-AbdallahLS #energy #fault #robust #statistics
Timing error statistics for energy-efficient robust DSP systems (RAA, YHL, NRS), pp. 285–288.
DATE-2011-KolpeZS #clustering #manycore #power management
Enabling improved power management in multicore processors through clustered DVFS (TK, AZ, SSS), pp. 293–298.
DATE-2011-EbrahimiMA #fault #named #safety
ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications (ME, SGM, HA), pp. 298–292.
DATE-2011-HameedFH #3d #adaptation #architecture #manycore #runtime
Dynamic thermal management in 3D multi-core architecture through run-time adaptation (FH, MAAF, JH), pp. 299–304.
DATE-2011-WagnerL #distributed #framework #hardware
Distributed hardware matcher framework for SoC survivability (IW, SLL), pp. 305–310.
DATE-2011-PanHHL #effectiveness
A cost-effective substantial-impact-filter based method to tolerate voltage emergencies (SP, YH, XH, XL), pp. 311–315.
DATE-2011-CabodiNQ #revisited #sequence
Interpolation sequences revisited (GC, SN, SQ), pp. 316–322.
DATE-2011-KengSV #automation #debugging
Automated debugging of SystemVerilog assertions (BK, SS, AGV), pp. 323–328.
DATE-2011-BradyHS
Counterexample-guided SMT-driven optimal buffer sizing (BAB, DEH, SAS), pp. 329–334.
DATE-2011-WangWT #approach #modelling #named #performance #scheduling #simulation
DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling (PCW, MHW, RST), pp. 335–340.
DATE-2011-LoCWT #modelling #performance #simulation
Cycle-count-accurate processor modeling for fast and accurate system-level simulation (CKL, LCC, MHW, RST), pp. 341–346.
DATE-2011-FuWT #approach #manycore #performance #simulation
A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems (CYF, MHW, RST), pp. 347–352.
DATE-2011-YehHWL #framework #platform #simulation
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method (YFY, CYH, CAW, HCL), pp. 353–358.
DATE-2011-WangCC #self
An all-digital built-in self-test technique for transfer function characterization of RF PLLs (PYW, HMC, KTC), pp. 359–364.
DATE-2011-MotaS #detection #testing
A true power detector for RF PA built-in calibration and testing (PFdM, JMdS), pp. 365–370.
DATE-2011-HashempourDTKHBX #fault #industrial #reduction #testing
Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example (HH, JD, BT, BK, CH, MvB, YX), pp. 371–376.
DATE-2011-SinghSG #generative #performance #testing #using
Testing of high-speed DACs using PRBS generation with “Alternate-Bit-Tapping” (MS, MS, SG), pp. 377–382.
DATE-2011-JuanGM #3d #evaluation #multi #process #statistics
Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations (DCJ, SG, DM), pp. 383–388.
DATE-2011-WeisWLB #3d #design
Design space exploration for 3D-stacked DRAMs (CW, NW, IL, LB), pp. 389–394.
DATE-2011-XuPM
Analytical heat transfer model for thermal through-silicon vias (HX, VFP, GDM), pp. 395–400.
DATE-2011-ChenLWH #3d #architecture #network
A new architecture for power network in 3D IC (HTC, HLL, ZCW, TH), pp. 401–406.
DATE-2011-CararaASM
Achieving composability in NoC-based MPSoCs through QoS management at software level (EC, GMA, GS, FGM), pp. 407–412.
DATE-2011-AsadiniaMTS #using
Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links (MA, MM, AT, HSA), pp. 413–418.
DATE-2011-WinterF #runtime #scheduling
Guaranteed service virtual channel allocation in NoCs for run-time task scheduling (MW, GF), pp. 419–424.
DATE-2011-NejadMG #quality
An FPGA bridge preserving traffic quality of service for on-chip network-based systems (ABN, MEM, KG), pp. 425–430.
DATE-2011-FettweisGK #towards
Entering the path towards terabit/s wireless links (GF, FG, SK), pp. 431–436.
DATE-2011-DupretTVAP
Smart imagers of the future (AD, MT, AV, LA, AP), pp. 437–442.
DATE-2011-WuDL #multi
Power-driven global routing for multi-supply voltage domains (THW, AD, JTL), pp. 443–448.
DATE-2011-YanC #multi
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance (JTY, ZWC), pp. 449–454.
DATE-2011-LuHCT #bound
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing (JL, VH, XC, BT), pp. 455–460.
DATE-2011-TsaiLCKCK #bound #on the
On routing fixed escaped boundary pins for high speed boards (TYT, RJL, CYC, CYK, HMC, YK), pp. 461–466.
DATE-2011-NalamCAC
Dynamic write limited minimum operating voltage for nanoscale SRAMs (SN, VC, RCA, BHC), pp. 467–472.
DATE-2011-GhasemazarP #architecture #multi #power management
Variation aware dynamic power management for chip multiprocessor architectures (MG, MP), pp. 473–478.
DATE-2011-HuangQ #constraints #energy #realtime
Leakage aware energy minimization for real-time systems under the maximum temperature constraint (HH, GQ), pp. 479–484.
DATE-2011-TinoK #architecture #generative #multi
Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures (AT, GNK), pp. 485–490.
DATE-2011-RahimiLKB #clustering #network
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters (AR, IL, MRK, LB), pp. 491–496.
DATE-2011-Al-DujailyMXYP #concurrent #detection #network #runtime #transitive #using
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks (RAD, TSTM, FX, AY, MP), pp. 497–502.
DATE-2011-MatsudaI #debugging #verification
Developing an integrated verification and debug methodology (AM, TI), pp. 503–504.
DATE-2011-EnemanCMMCMMBHP #estimation #multi
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations (GE, JC, VM, DM, MC, KDM, AM, EB, TH, GVdP), pp. 505–506.
DATE-2011-KapoorHT #case study #experience #power management #verification
Power management verification experiences in Wireless SoCs (BK, AH, PT), pp. 507–508.
DATE-2011-YipYLD #challenge #design #memory management #mobile
Challenges in designing high speed memory subsystem for mobile applications (TGY, PY, ML, DD), pp. 509–510.
DATE-2011-MazzilloFFMRZ #detection
Solid state photodetectors for nuclear medical imaging applications (MM, PGF, EF, AM, MR, RZ), pp. 511–512.
DATE-2011-BernardiGSB #fault #self #testing
Fault grading of software-based self-test procedures for dependable automotive applications (PB, MG, ES, OB), pp. 513–514.
DATE-2011-JahnFH #adaptation #architecture #migration #multi #named #runtime
CARAT: Context-aware runtime adaptive task migration for multi core architectures (JJ, MAAF, JH), pp. 515–520.
DATE-2011-BaiocchiC #embedded
Demand code paging for NAND flash in MMU-less embedded systems (JB, BRC), pp. 517–532.
DATE-2011-FalkZHT #algorithm #clustering #data flow #embedded #performance #rule-based #synthesis
A rule-based static dataflow clustering algorithm for efficient embedded software synthesis (JF, CZ, CH, JT), pp. 521–526.
DATE-2011-GizopoulosPARHSMBV #architecture #detection #fault #manycore #online
Architectures for online error detection and recovery in multicore processors (DG, MP, SVA, PR, SKSH, DJS, AM, AB, XV), pp. 533–538.
DATE-2011-ZhaoDX #3d #design #energy #fine-grained #scalability
An energy-efficient 3D CMP design with fine-grained voltage scaling (JZ, XD, YX), pp. 539–542.
DATE-2011-CabodiN #model checking #multi
Optimized model checking of multiple properties (GC, SN), pp. 543–546.
DATE-2011-KimCY #distributed #predict #simulation
A new distributed event-driven gate-level HDL simulation by accurate prediction (DK, MJC, SY), pp. 547–550.
DATE-2011-BalasubramanianSMNDKMPPVT #low cost #power management #robust
Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system (LB, PS, RKM, PN, RKD, ADK, SM, SP, HP, RCV, ST), pp. 551–554.
DATE-2011-LafiLJ #3d #configuration management #framework #platform
A 3D reconfigurable platform for 4G telecom applications (WL, DL, AAJ), pp. 555–558.
DATE-2011-KobayashiH #analysis #correlation #power management
An LOCV-based static timing analysis considering spatial correlations of power supply variations (SK, KH), pp. 559–562.
DATE-2011-TraulsenAH #c #compilation
Compiling SyncCharts to Synchronous C (CT, TA, RvH), pp. 563–566.
DATE-2011-ChangMFWHYN #architecture #hardware #hybrid #optimisation
Optimization of stateful hardware acceleration in hybrid architectures (XC, YM, HF, KW, RH, HY, TN), pp. 567–570.
DATE-2011-ChungCCK
Formal reset recovery slack calculation at the register transfer level (CNC, CWC, KHC, SYK), pp. 571–574.
DATE-2011-FourmigueBNAO #3d #architecture #evaluation #multi
Multi-granularity thermal evaluation of 3D MPSoC architectures (AF, GB, GN, EMA, IO), pp. 575–578.
DATE-2011-KeezerG #synthesis
Two methods for 24 Gbps test signal synthesis (DCK, CEG), pp. 579–582.
DATE-2011-ChenLCP #3d #design #memory management #named
3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers (YCC, HL, YC, REP), pp. 583–586.
DATE-2011-ChenLH #3d #architecture #towards
Architectural exploration of 3D FPGAs towards a better balance between area and delay (CIC, BCL, JDH), pp. 587–590.
DATE-2011-PorquetGS #architecture #flexibility #memory management #named
NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs (JP, AG, CS), pp. 591–594.
DATE-2011-BilgicPGB #industrial #power management
Low-power smart industrial control (AB, VP, MG, FB), pp. 595–599.
DATE-2011-WohSDKSBM #power management
Low power interconnects for SIMD computers (MW, SS, RGD, DK, DS, DB, TNM), pp. 600–605.
DATE-2011-Kauppinen #smarttech
Wireless innovations for smartphones (HK), p. 606.
DATE-2011-Struzyna #clustering #constraints
Flow-based partitioning and position constraints in VLSI placement (MS), pp. 607–612.
DATE-2011-ChenZD #optimisation
Integrated circuit white space redistribution for temperature optimization (YC, HZ, RPD), pp. 613–618.
DATE-2011-ChenY #design
Timing-constrained I/O buffer placement for flip-chip designs (ZWC, JTY), pp. 619–624.
DATE-2011-XueJZZ #evaluation #performance
Floorplanning exploration and performance evaluation of a new Network-on-Chip (LX, WJ, QZ, YZ), pp. 625–630.
DATE-2011-RaiYBCT #analysis #realtime #worst-case
Worst-case temperature analysis for real-time systems (DR, HY, IB, JJC, LT), pp. 631–636.
DATE-2011-TsengHWFC #black box #compilation #library #modelling #power management
Black-box leakage power modeling for cell library and SRAM compiler (CKT, SYH, CCW, SCF, JJC), pp. 637–642.
DATE-2011-HsuL #optimisation
Clock gating optimization with delay-matching (SJH, RBL), pp. 643–648.
DATE-2011-ReddyCBJ #complexity #power management
A low complexity stopping criterion for reducing power consumption in turbo decoders (PR, FC, AB, MJ), pp. 649–654.
DATE-2011-ParkYL #novel #power management
A novel tag access scheme for low power L2 cache (HP, SY, SL), pp. 655–660.
DATE-2011-StranoGLFGB #architecture #scalability #self
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture (AS, CGR, DL, MF, MEG, DB), pp. 661–666.
DATE-2011-KakoeeBB #communication #named #network #reliability
ReliNoC: A reliable network for priority-based on-chip communication (MRK, VB, LB), pp. 667–672.
DATE-2011-ChouM #multi #named #platform #resource management
FARM: Fault-aware resource management in NoC-based multiprocessor platforms (CLC, RM), pp. 673–678.
DATE-2011-YeHL #fault #multi #on the #using
On diagnosis of multiple faults using compacted responses (JY, YH, XL), pp. 679–684.
DATE-2011-LiuX #debugging #multi #on the
On multiplexed signal tracing for post-silicon debug (XL, QX), pp. 685–690.
DATE-2011-GaoHL #debugging #multi
Eliminating data invalidation in debugging multiple-clock chips (JG, YH, XL), pp. 691–696.
DATE-2011-GeunsBBC #parallel #source code
Parallelization of while loops in nested loop programs for shared-memory multiprocessor systems (SJG, MJGB, TB, HC), pp. 697–702.
DATE-2011-WuWWZLXY #architecture #parallel #programming
Gemma in April: A matrix-like parallel programming architecture on OpenCL (TW, DW, YW, XZ, HL, NX, HY), pp. 703–708.
DATE-2011-MuWLLZCXD #embedded #performance
Evaluating the potential of graphics processors for high performance embedded computing (SM, CW, ML, DL, MZ, XC, XX, YD), pp. 709–714.
DATE-2011-LeupersEMSTC #manycore #platform #towards
Virtual Manycore platforms: Moving towards 100+ processor cores (RL, LE, GM, FS, NPT, XC), pp. 715–720.
DATE-2011-Winterholer #debugging #embedded #requirements
Embedded software debug and test: Needs and requirements for innovations in debugging (MW), p. 721.
DATE-2011-RabaeyMCSTGWW #communication
Powering and communicating with mm-size implants (JMR, MM, DC, CS, CT, SG, MW, DW), pp. 722–727.
DATE-2011-FoucauldDDC
An antenna-filter codesign for cardiac implants (EdF, JBD, CD, PC), pp. 728–733.
DATE-2011-XuDJX #design
Design implications of memristor-based RRAM cross-point structures (CX, XD, NPJ, YX), pp. 734–739.
DATE-2011-YangM #design #robust
Robust 6T Si tunneling transistor SRAM design (XY, KM), pp. 740–745.
DATE-2011-HuXZTS #energy #hybrid #memory management #performance #towards
Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory (JH, CJX, QZ, WCT, EHMS), pp. 746–751.
DATE-2011-SterponeCMWF #configuration management #power management
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.
DATE-2011-HeGO #design #energy
Controlled timing-error acceptance for low energy IDCT design (KH, AG, MO), pp. 758–763.
DATE-2011-AvinashENPP #design #energy #probability
Energy parsimonious circuit design through probabilistic pruning (LA, CCE, JLN, KVP, CP), pp. 764–769.
DATE-2011-LuPRR #energy #optimisation
Stage number optimization for switched capacitor power converters in micro-scale energy harvesting (CL, SPP, VR, KR), pp. 770–775.
DATE-2011-OnizawaMH #communication #monitoring
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring (NO, AM, TH), pp. 776–781.
DATE-2011-HendryCCB #design #named #network #specification
VANDAL: A tool for the design specification of nanophotonic networks (GH, JC, LPC, KB), pp. 782–787.
DATE-2011-BeuxTONBP #architecture #design
Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology (SLB, JT, IO, GN, GB, PGP), pp. 788–793.
DATE-2011-DrmanacSWWA #multi #optimisation #parametricity #predict #testing
Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits (DGD, NS, LW, LCW, MSA), pp. 794–799.
DATE-2011-SreedharK #design #identification #on the #process
On design of test structures for lithographic process corner identification (AS, SK), pp. 800–805.
DATE-2011-RekikADMN #development #evaluation
An electrical test method for MEMS convective accelerometers: Development and evaluation (AAR, FA, ND, FM, PN), pp. 806–811.
DATE-2011-KuppSM #correlation
Correlating inline data with final test outcomes in analog/RF devices (NK, MS, YM), pp. 812–817.
DATE-2011-LopezMBPGE #design #interface #process #programmable
Systematic design of a programmable low-noise CMOS neural interface for cell activity recording (CML, SM, CB, RP, GGEG, WE), pp. 818–823.
DATE-2011-KanounMKA #monitoring #realtime
A real-time compressed sensing-based personal electrocardiogram monitoring system (KK, HM, NK, DA), pp. 824–829.
DATE-2011-BartoliniCTB #distributed #energy #multi #predict #self
A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicores (AB, MC, AT, LB), pp. 830–835.
DATE-2011-CarliBBR #effectiveness #energy #multi #power management
An effective multi-source energy harvester for low power applications (DC, DB, LB, MR), pp. 836–841.
DATE-2011-PerathonerLT #analysis #component #performance
Composing heterogeneous components for system-wide performance analysis (SP, KL, LT), pp. 842–847.
DATE-2011-VissersNN #interface #realtime #synthesis #tool support #using
Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools (KAV, SN, JN), pp. 848–850.
DATE-2011-AkessonG #architecture #integration #memory management #modelling #predict
Architectures and modeling of predictable memory controllers for improved system integration (BA, KG), pp. 851–856.
DATE-2011-WolfG #integration #predict
SoC infrastructures for predictable system integration (PvdW, JG), pp. 857–862.
DATE-2011-ShinDLWJ
Early chip planning cockpit (JS, JAD, GL, AJW, CLJ), pp. 863–866.
DATE-2011-RahmanTS #reduction
Power reduction via near-optimal library-based cell-size selection (MR, HT, CS), pp. 867–870.
DATE-2011-KangD #classification #gpu #metaprogramming #scalability
Scalable packet classification via GPU metaprogramming (KK, YSD), pp. 871–874.
DATE-2011-ShinKSCWP #hybrid
Battery-supercapacitor hybrid system for high-rate pulsed load applications (DS, YK, JS, NC, YW, MP), pp. 875–878.
DATE-2011-PontarelliOSZ #feedback
Feedback based droop mitigation (SP, MO, AS, KZ), pp. 879–882.
DATE-2011-QiaoCL
A 0.964mW digital hearing aid system (PQ, HC, ML), pp. 883–886.
DATE-2011-MirhoseiniK #energy #hybrid #optimisation #performance
HypoEnergy. Hybrid supercapacitor-battery power-supply optimization for Energy efficiency (AM, FK), pp. 887–890.
DATE-2011-TendulkarPNKNK #communication #hardware #runtime
Fine-grain OpenMP runtime support with explicit communication hardware primitives (PT, VP, GN, SGK, DSN, MK), pp. 891–894.
DATE-2011-MiyaseWAFYK #generative #testing
Transition-Time-Relation based capture-safety checking for at-speed scan test generation (KM, XW, MA, HF, YY, SK), pp. 895–898.
DATE-2011-LandrockOCKA #2d #3d #integration
2D and 3D integration with organic and silicon electronics (CKL, BO, YC, BK, JA), pp. 899–904.
DATE-2011-WeddellMA #power management
Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodes (ASW, GVM, BMAH), pp. 905–908.
DATE-2011-ChaixAZN #adaptation #concurrent #fault tolerance
A fault-tolerant deadlock-free adaptive routing for on chip interconnects (FC, DA, NEZ, MN), pp. 909–912.
DATE-2011-GoswamiSC #communication #cyber-physical #hybrid #protocol #re-engineering
Re-engineering cyber-physical control applications for hybrid communication protocols (DG, RS, SC), pp. 914–919.
DATE-2011-MontagA #precise #realtime
Precise WCET calculation in highly variant real-time systems (PM, SA), pp. 920–925.
DATE-2011-SchenkelaarsVG #network #scheduling
Optimal scheduling of switched FlexRay networks (TS, BV, KG), pp. 926–931.
DATE-2011-ChanSGK #on the
On the efficacy of NBTI mitigation techniques (TBC, JS, PG, RK), pp. 932–937.
DATE-2011-CalimeraLMP #architecture
Partitioned cache architectures for reduced NBTI-induced aging (AC, ML, EM, MP), pp. 938–943.
DATE-2011-KrauseP #adaptation
Adaptive voltage over-scaling for resilient applications (PKK, IP), pp. 944–949.
DATE-2011-MohapatraCRR #approximate #design
Design of voltage-scalable meta-functions for approximate computing (DM, VKC, AR, KR), pp. 950–955.
DATE-2011-PhadkeN #memory management
MLP aware heterogeneous memory system (SP, SN), pp. 956–961.
DATE-2011-FerreiraBCMM #algorithm #process
Impact of process variation on endurance algorithms for wear-prone memories (APF, SB, BRC, RGM, DM), pp. 962–967.
DATE-2011-WangZHLL #memory management
Flex memory: Exploiting and managing abundant off-chip optical bandwidth (YW, LZ, YH, HL, XL), pp. 968–973.
DATE-2011-GilaniKS #memory management #optimisation
Scratchpad memory optimizations for digital signal processing applications (SZG, NSK, MJS), pp. 974–979.
DATE-2011-VatajeluF #analysis #in memory #memory management #robust
Robustness analysis of 6T SRAMs in memory retention mode under PVT variations (EIV, JF), pp. 980–985.
DATE-2011-AlordaTBS #embedded #optimisation #using
Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation (BA, GT, SAB, JS), pp. 986–991.
DATE-2011-LiZY
Proactive recovery for BTI in high-k SRAM cells (LL, YZ, JY), pp. 992–997.
DATE-2011-Cilardo #configuration management #hardware
The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1 (AC), pp. 998–1003.
DATE-2011-MeynardRFGHD
Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques (OM, DR, FF, SG, NH, JLD), pp. 1004–1009.
DATE-2011-MaW #detection #fault #low cost #named
LOEDAR: A low cost error detection and recovery scheme for ECC (KM, KW), pp. 1010–1015.
DATE-2011-KaraklajicFSV #detection #fault #low cost #using
Low-cost fault detection method for ECC using Montgomery powering ladder (DK, JF, JMS, IV), pp. 1016–1021.
DATE-2011-Sifakis #component #design #tool support
Methods and tools for component-based system design (JS), p. 1022.
DATE-2011-DammHJPS #architecture #component #contract #design #integration #specification #testing #using
Using contract-based component specifications for virtual integration testing and architecture design (WD, HH, BJ, TP, IS), pp. 1023–1028.
DATE-2011-LeeS #component #design
Component-based design for the future (EAL, ALSV), p. 1029.
DATE-2011-DOrazioVD #challenge #network #state of the art
Sensor networks on the car: State of the art and future challenges (LD, FV, MD), pp. 1030–1035.
DATE-2011-MatischekHGH #communication #realtime
Real-time wireless communication in automotive applications (RM, TH, CG, JH), pp. 1036–1041.
DATE-2011-MahlknechtKGW #communication #energy
Wireless communication and energy harvesting in automobiles (SM, TJK, CG, LW), pp. 1042–1047.
DATE-2011-Brown #power management #roadmap
Power management trends in portable consumer applications (JB), pp. 1048–1052.
DATE-2011-LiuS #continuation #optimisation #performance
An efficient mask optimization method based on homotopy continuation technique (FL, XS), pp. 1053–1058.
DATE-2011-RoyBC
Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips (SR, BBB, KC), pp. 1059–1064.
DATE-2011-WangNKWRLMB #configuration management #using
High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches (XW, SN, ARK, FGW, SR, THL, MM, SB), pp. 1065–1070.
DATE-2011-ZhangHYG #case study #interface #reliability
Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface (WZ, JH, SY, PG), pp. 1071–1076.
DATE-2011-SoekenWD #aspect-oriented #modelling #uml #verification
Verifying dynamic aspects of UML models (MS, RW, RD), pp. 1077–1082.
DATE-2011-BaiDCD #automation #modelling #network #performance
Automated construction of fast and accurate system-level models for wireless sensor networks (LSB, RPD, PHC, PAD), pp. 1083–1088.
DATE-2011-IndrusiakS #performance #transaction
Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration (LSI, OMdS), pp. 1089–1094.
DATE-2011-CassidyYZA #design
A high-level analytical model for application specific CMP design exploration (AC, KY, HZ, AGA), pp. 1095–1100.
DATE-2011-LiuHRG #optimisation #process #using
Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model (BL, YH, PR, GGEG), pp. 1101–1106.
DATE-2011-ErbP #analysis #performance
A method for fast jitter tolerance analysis of high-speed PLLs (SE, WP), pp. 1107–1112.
DATE-2011-AadithyaDVR #modelling #named #random #simulation
SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs (KVA, AD, SV, JSR), pp. 1113–1118.
DATE-2011-HuangRBK #adaptation #runtime #workflow
A workflow for runtime adaptive task allocation on heterogeneous MPSoCs (JH, AR, CB, AK), pp. 1119–1134.
DATE-2011-PasettiCTSDSF
Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects (GP, NC, FT, RS, PD, SS, LF), pp. 1119–1120.
DATE-2011-BonannoBS #analysis #energy #modelling #monitoring #optimisation #tool support
Energy analysis methods and tools for modelling and Optimizing monitoring tyre systems (AB, AB, MS), pp. 1121–1122.
DATE-2011-AcquavivaPOS #power management #reliability
System level techniques to improve reliability in high power microcontrollers for automotive applications (AA, MP, MO, MS), pp. 1123–1124.
DATE-2011-GrammatikakisPSP #estimation #using
System-level power estimation methodology using cycle- and bit-accurate TLM (MDG, SP, JPS, CP), pp. 1125–1126.
DATE-2011-RinaudoGCMP #approach #design #energy #performance #power management
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems (SR, GG, AC, AM, MP), pp. 1127–1128.
DATE-2011-KongYD #clustering #energy #multi #realtime #scheduling
Energy-efficient scheduling of real-time tasks on cluster-based multicores (FK, WY, QD), pp. 1135–1140.
DATE-2011-BathenD #distributed #embedded #named #power management #reliability
E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories (LADB, NDD), pp. 1141–1146.
DATE-2011-KunduS #design #modelling #process
Modeling manufacturing process variation for design and test (SK, AS), pp. 1147–1152.
DATE-2011-MirandaZDR #logic #modelling #variability
Variability aware modeling for yield enhancement of SRAM and logic (MM, PZ, PD, PR), pp. 1153–1158.
DATE-2011-AitkenYF #correlation #modelling #parametricity
Correlating models and silicon for improved parametric yield (RA, GY, DF), pp. 1159–1163.
DATE-2011-AmoryOMML #energy #using
Evaluating energy consumption of homogeneous MPSoCs using spare tiles (AMA, LO, CAMM, FGM, ML), pp. 1164–1167.
DATE-2011-KunzGW #hardware #memory management #performance #transaction
Improving the efficiency of a hardware transactional memory on an NoC-based MPSoC (LK, GG, FRW), pp. 1168–1171.
DATE-2011-ChandraA
Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown (VC, RCA), pp. 1172–1175.
DATE-2011-AliCMB #encryption #hardware #multi #security
Multi-level attacks: An emerging security concern for cryptographic hardware (SA, RSC, DM, SB), pp. 1176–1179.
DATE-2011-ThapliyalR #design
A new reversible design of BCD adder (HT, NR), pp. 1180–1183.
DATE-2011-FunchalM #framework #modelling #named #simulation #transaction
jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip (GF, MM), pp. 1184–1187.
DATE-2011-NarayananZT #correctness #pattern matching #process #using
Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching (RN, MHZ, ST), pp. 1188–1191.
DATE-2011-BeltrameN #algorithm #design #multi #platform
A multi-objective decision-theoretic exploration algorithm for platform-based design (GB, GN), pp. 1192–1195.
DATE-2011-PenolazziSH #energy #multi #performance #predict
Predicting bus contention effects on energy and performance in multi-processor SoCs (SP, IS, AH), pp. 1196–1199.
DATE-2011-HuangWSLXL #embedded #low cost
A specialized low-cost vectorized loop buffer for embedded processors (LH, ZW, LS, HL, NX, CL), pp. 1200–1203.
DATE-2011-WilleKD #scalability
Determining the minimal number of lines for large reversible circuits (RW, OK, RD), pp. 1204–1207.
DATE-2011-VidalLGDG #configuration management #design #implementation #uml
Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation (JV, FdL, GG, JPD, SG), pp. 1208–1211.
DATE-2011-FerentD #automation #design #similarity
A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design features (CF, AD), pp. 1212–1217.
DATE-2011-Wang #coordination #gpu #kernel #power management
Coordinate strip-mining and kernel fusion to lower power consumption on GPU (GW), pp. 1218–1219.
DATE-2011-BruschiPRS #automaton #performance
An efficient Quantum-Dot Cellular Automata adder (FB, FP, VR, DS), pp. 1220–1223.
DATE-2011-AgarwalWG #comprehension
Understanding the role of buildings in a smart microgrid (YA, TW, RKG), pp. 1224–1229.
DATE-2011-Papa
Smart systems at ST (CP), p. 1230.
DATE-2011-RoyRM #algorithm #modelling #performance
Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs (SSR, CR, DM), pp. 1231–1236.
DATE-2011-KesturDN #named #streaming
SHARC: A streaming model for FPGA accelerators and its application to Saliency (SK, DD, VN), pp. 1237–1242.
DATE-2011-SafarESS #configuration management #pipes and filters #satisfiability
A reconfigurable, pipelined, conflict directed jumping search SAT solver (MS, MWEK, MS, AS), pp. 1243–1248.
DATE-2011-MeyerGCLS #cost analysis #execution #safety #using
Reducing the cost of redundant execution in safety-critical systems using relaxed dedication (BHM, NJG, BHC, JL, KS), pp. 1249–1254.
DATE-2011-YangO #adaptation #flexibility #manycore
Frugal but flexible multicore topologies in support of resource variation-driven adaptivity (CY, AO), pp. 1255–1260.
DATE-2011-ShafiqueBAH #configuration management #manycore #resource management #runtime
Minority-Game-based resource allocation for run-time reconfigurable multi-core processors (MS, LB, WA, JH), pp. 1261–1266.
DATE-2011-WangKAWMA #energy #simulation #using
Accelerated simulation of tunable vibration energy harvesting systems using a linearised state-space technique (LW, TJK, BMAH, ASW, GVM, INAG), pp. 1267–1272.
DATE-2011-ZaidiGH #simulation #specification
Simulation based tuning of system specification (YZ, CG, JH), pp. 1273–1278.
DATE-2011-ZhaoK #component #distributed
An extension to SystemC-A to support mixed-technology systems with distributed components (CZ, TJK), pp. 1278–1284.
DATE-2011-MaricauG #analysis #probability #reliability
Stochastic circuit reliability analysis (EM, GGEG), pp. 1285–1290.
DATE-2011-EggersglusD #fault #generative #optimisation #pseudo #testing #using
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization (SE, RD), pp. 1291–1296.
DATE-2011-Pomeranz #functional #generative #testing
Built-in generation of functional broadside tests (IP), pp. 1297–1302.
DATE-2011-KochteW #evaluation #fault #satisfiability
SAT-based fault coverage evaluation in the presence of unknown values (MAK, HJW), pp. 1303–1308.
DATE-2011-JhaLMR #simulation #statistics #trade-off #verification
When to stop verification?: Statistical trade-off between expected loss and simulation cost (SKJ, CJL, SM, SR), pp. 1309–1314.
DATE-2011-HausmansBC #data flow #graph
Resynchronization of Cyclo-Static Dataflow graphs (JPHMH, MJGB, HC), pp. 1315–1320.
DATE-2011-ChiuSH #constraints #pipes and filters #precedence #realtime #streaming #synthesis
Pipeline schedule synthesis for real-time streaming tasks with inter/intra-instance precedence constraints (YSC, CSS, SHH), pp. 1321–1326.
DATE-2011-ClermidyDDLV #3d #embedded #manycore
3D Embedded multi-core: Some perspectives (FC, FD, DD, WL, PV), pp. 1327–1332.
DATE-2011-KimYLAJ #3d #analysis #embedded #mobile #performance
A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC (DK, SY, SL, JHA, HJ), pp. 1333–1338.
DATE-2011-CroneBCDER #state of the art #verification
State of the art verification methodologies in 2015 (AC, OB, CC, BD, VE, MR), p. 1339.
DATE-2011-Yakovlev #energy
Energy-modulated computing (AY), pp. 1340–1345.
DATE-2011-YoonLJPKPC #configuration management #embedded #incremental #named
I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics (JWY, JL, JJ, SP, YK, YP, DC), pp. 1346–1351.
DATE-2011-LangeWK #configuration management #memory management #multi
MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers (HL, TW, AK), pp. 1352–1357.
DATE-2011-AnjamNW #multi #runtime
Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor (FA, MN, SW), pp. 1358–1363.
DATE-2011-ZhiLZYZZ #algorithm #multi #performance #scheduling
An efficient algorithm for multi-domain clock skew scheduling (YZ, WSL, HZ, CY, HZ, XZ), pp. 1364–1369.
DATE-2011-AgyekumN #communication #hardware #robust
A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication (MYA, SMN), pp. 1370–1375.
DATE-2011-LiMY #independence
Redressing timing issues for speed-independent circuits in deep submicron age (YL, TSTM, AY), pp. 1376–1381.
DATE-2011-KondratyevLMW #pipes and filters #synthesis
Realistic performance-constrained pipelining in high-level synthesis (AK, LL, MM, YW), pp. 1382–1387.
DATE-2011-DraneC #optimisation
Optimisation of mutually exclusive arithmetic sum-of-products (TD, GAC), pp. 1388–1393.
DATE-2011-KelleyWDSRH #generative
Intermediate representations for controllers in chip generators (KK, MW, AD, PS, SR, MH), pp. 1394–1399.
DATE-2011-BarrioMMMH #optimisation
Power optimization in heterogenous datapaths (AADB, SOM, MCM, JMM, RH), pp. 1400–1405.
DATE-2011-SinhaP #representation #state machine #synthesis
Abstract state machines as an intermediate representation for high-level synthesis (RS, HDP), pp. 1406–1411.
DATE-2011-ZadeganICL #automation #design
Design automation for IEEE P1687 (FGZ, UI, GC, EL), pp. 1412–1417.
DATE-2011-ButtrickK #3d #network #on the #testing #using
On testing prebond dies with incomplete clock networks in a 3D IC using DLLs (MB, SK), pp. 1418–1423.
DATE-2011-KumarRPB #3d #clustering #testing
Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing (AK, SMR, IP, BB), pp. 1424–1429.
DATE-2011-ArslanO #adaptation #effectiveness #learning #optimisation #realtime
Adaptive test optimization through real time learning of test effectiveness (BA, AO), pp. 1430–1435.
DATE-2011-AkinBNRSA #algorithm #implementation #parallel
A high-performance parallel implementation of the Chambolle algorithm (AA, IB, AAN, VR, MDS, DA), pp. 1436–1441.
DATE-2011-KyrkouTT #detection #hardware
Depth-directed hardware object detection (CK, CT, TT), pp. 1442–1447.
DATE-2011-ZattSBH #architecture #estimation #hardware #parallel #pipes and filters #throughput #video
Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding (BZ, MS, SB, JH), pp. 1448–1453.
DATE-2011-MicheliGBVC #framework #platform
An integrated platform for advanced diagnostics (GDM, SSG, CB, FV, SC), pp. 1454–1459.
DATE-2011-BeutelBFKZT #named
X-SENSE: Sensing in extreme environments (JB, BB, FF, MK, MZ, LT), pp. 1460–1465.
DATE-2011-SabrySATLSBTBM #3d #design #towards
Towards thermally-aware design of 3D MPSoCs with inter-tier cooling (MMS, AS, DA, YT, YL, SS, NB, JRT, TB, BM), pp. 1466–1471.
DATE-2011-HuangDEB #collaboration #communication #framework #platform
A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch Initiative (QH, CD, CE, TB), pp. 1472–1473.
DATE-2011-GielenMW #analysis #reliability
Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation (GGEG, EM, PHNDW), pp. 1474–1479.
DATE-2011-AsenovBC #aspect-oriented #statistics
Statistical aspects of NBTI/PBTI and impact on SRAM yield (AA, ARB, BC), pp. 1480–1485.
DATE-2011-RemondNBM #approach #design #empirical #process #simulation
Mathematical approach based on a “Design of Experiment” to simulate process variations (ER, EN, CB, RM), pp. 1486–1490.
DATE-2011-ShanbhagS #design
System-assisted analog mixed-signal design (NRS, ACS), pp. 1491–1496.
DATE-2011-ShahRK #bound #latency #performance
Priority division: A high-speed shared-memory bus arbitration with bounded latency (HS, AR, AK), pp. 1497–1500.
DATE-2011-BeserraMSC #modelling #network
System-level modeling of a mixed-signal System on Chip for Wireless Sensor Networks (GSB, JEGdM, AMS, JCdC), pp. 1500–1504.
DATE-2011-SunYW #co-evolution #design #framework #network #uml
A UML 2-based hardware-software co-design framework for body sensor network applications (ZS, CTY, WFW), pp. 1505–1508.
DATE-2011-GolaniB #multi #pipes and filters
An area-efficient multi-level single-track pipeline template (PG, PAB), pp. 1509–1512.
DATE-2011-AnsaloniPTD #array #configuration management #scheduling
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays (GA, LP, KT, ND), pp. 1513–1516.
DATE-2011-KamalAP
Timing variation-aware custom instruction extension technique (MK, AAK, MP), pp. 1517–1520.
DATE-2011-NigamTZBM #nondeterminism #pseudo #representation
Pseudo circuit model for representing uncertainty in waveforms (AN, QT, AZ, MB, NvdM), pp. 1521–1524.
DATE-2011-VasicekS #optimisation
A global postsynthesis optimization method for combinational circuits (ZV, LS), pp. 1525–1528.
DATE-2011-TsukiyamaF #algorithm #analysis #statistics
An algorithm to improve accuracy of criticality in statistical static timing analysis (ST, MF), pp. 1529–1532.
DATE-2011-WelpK #approach #markov #process #synthesis
An approach for dynamic selection of synthesis transformations based on Markov Decision Processes (TW, AK), pp. 1533–1536.
DATE-2011-MerrettAWZRMRLFA #analysis #modelling #monte carlo #performance #statistics #variability
Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis (MM, PA, YW, MZ, DR, CM, SR, ZL, SBF, AA), pp. 1537–1540.
DATE-2011-MeyerNHBSGSB #configuration management #performance #using
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration (JM, JN, MH, LB, OS, RMG, RS, JB), pp. 1542–1547.
DATE-2011-DragomirB #architecture #configuration management
Loop distribution for K-loops on Reconfigurable Architectures (OSD, KB), pp. 1548–1553.
DATE-2011-AhmedSBH #configuration management #multi #named #runtime
mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions (WA, MS, LB, JH), pp. 1554–1559.
DATE-2011-ZukoskiCM #logic #synthesis
Reliability-driven don’t care assignment for logic synthesis (AZ, MRC, KM), pp. 1560–1565.
DATE-2011-ShinG #fault
A new circuit simplification method for error tolerant applications (DS, SKG), pp. 1566–1571.
DATE-2011-WuM #analysis #optimisation
Aging-aware timing analysis and optimization considering path sensitization (KCW, DM), pp. 1572–1577.
DATE-2011-LuJTL #architecture #parametricity #performance #simulation
Efficient parameter variation sampling for architecture simulations (FL, RJ, GT, SL), pp. 1578–1583.
DATE-2011-KimCSY #modelling #parallel #performance #simulation #using
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models (DK, MJC, KS, SY), pp. 1584–1589.
DATE-2011-AdirCLNSZMS #validation #verification
A unified methodology for pre-silicon verification and post-silicon validation (AA, SC, SL, AN, GS, AZ, CM, JS), pp. 1590–1595.
DATE-2011-LiuV #analysis #generative #performance #source code #validation
Efficient validation input generation in RTL by hybridized source code analysis (LL, SV), pp. 1596–1601.
DATE-2011-BarceloGBS #estimation #performance #scalability
An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation (SB, XG, SAB, JS), pp. 1602–1607.
DATE-2011-ChenKZBSNS
A confidence-driven model for error-resilient computing (CHC, YK, ZZ, DB, DS, HN, SS), pp. 1608–1613.
DATE-2011-NicolaidisBZ
Eliminating speed penalty in ECC protected memories (MN, TB, NEZ), pp. 1614–1619.
DATE-2011-RossiTSM #analysis #fault #memory management #performance #reliability
Error correcting code analysis for cache memory high reliability and performance (DR, NT, MS, CM), pp. 1620–1625.
DATE-2011-GhermanMECB #concurrent #fault #predict #self
Error prediction based on concurrent self-test and reduced slack time (VG, JM, SE, SC, YB), pp. 1626–1631.
DATE-2011-SreedharK11a #security
Physically unclonable functions for embeded security based on lithographic variation (AS, SK), pp. 1632–1637.
DATE-2011-ZhangT #detection #hardware #named #network
RON: An on-chip ring oscillator network for hardware Trojan detection (XZ, MT), pp. 1638–1643.
DATE-2011-MedwedM #detection #fault #logic
Arithmetic logic units with high error detection rates to counteract fault attacks (MM, SM), pp. 1644–1649.
DATE-2011-ChenGSS #analysis #performance
Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers (ZC, XG, AS, PS), pp. 1650–1655.
DATE-2011-PandeCPMBMG #energy #performance #platform #question
Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms? (PPP, FC, DP, IM, PB, RM, AG), pp. 1656–1661.
DATE-2011-MiteaMHJ #automation #constraints #synthesis
Automated constraint-driven topology synthesis for analog circuits (OM, MM, LH, PJ), pp. 1662–1665.
DATE-2011-SommerKHSS #automation #design #generative #network
A new method for automated generation of compensation networks — The EDA Designer Finger (RS, DK, EH, ES, CS), pp. 1666–1672.
DATE-2011-BoosNSHHGKS #analysis
Strategies for initial sizing and operating point analysis of analog circuits (VB, JN, MS, SH, SH, HG, DK, RS), pp. 1672–1674.
DATE-2011-GraupnerJW #approach #design #generative #layout #optimisation
Generator based approach for analog circuit and layout design and optimization (AG, RJ, RW), pp. 1675–1680.

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