BibSLEIGH — Maciej_J

Travelled to:

5 × Germany
6 × France
6 × USA

Collaborated with:

P.Kalla Z.Zeng E.Kinnen D.Gomez-Prado S.Yang C.Yang D.Kim J.Guillot E.Boutillon T.B.Ahmad D.A.Joy Q.Ren S.Askar R.Tessier V.Singhal J.Shen M.Davio K.Shim S.Park S.Cho Q.Zhang I.G.Harris B.Rouzeyre C.Huang C.Yu W.Brown D.Liu A.Rossi

Talks about:

level (6) use (6) simul (4) gate (4) transform (3) diagram (3) taylor (3) expans (3) assign (3) state (3)

Person: Maciej J. Ciesielski

DBLP: Ciesielski:Maciej_J=

Contributed to:

2015

2014

2013

2011

2009

2007

2006

2004

2003

2002

2001

2000

1999

1991

1982

1981

Wrote 20 papers:

DAC-2015-CiesielskiYBLR #verification: Verification of gate-level arithmetic circuits by function extraction (MJC, CY, WB, DL, AR), p. 6.
DATE-2014-AhmadC #performance #predict #simulation: Fast STA prediction-based gate-level timing simulation (TBA, MJC), pp. 1–6.
DATE-2013-Gomez-PradoCT #latency #optimisation #using: FPGA latency optimization using system-level transformations and DFG restructuring (DGP, MJC, RT), pp. 1553–1558.
DATE-2011-KimCSY #modelling #parallel #performance #simulation #using: Temporal parallel simulation: A fast gate-level HDL simulation using higher level models (DK, MJC, KS, SY), pp. 1584–1589.
DATE-2011-KimCY #distributed #predict #simulation: A new distributed event-driven gate-level HDL simulation by accurate prediction (DK, MJC, SY), pp. 547–550.
DATE-2009-Gomez-PradoRCGB #data flow #graph #hardware #implementation #optimisation: Optimizing data flow graphs to minimize hardware implementation (DGP, QR, MJC, JG, EB), pp. 117–122.
DATE-2007-CiesielskiAGGB #data flow #diagrams #using: Data-flow transformations using Taylor expansion diagrams (MJC, SA, DGP, JG, EB), pp. 455–460.
DATE-2006-GuillotBRCGA #diagrams #performance #using: Efficient factorization of DSP transforms using taylor expansion diagrams (JG, EB, QR, MJC, DGP, SA), pp. 754–755.
DAC-2004-ParkCYC #power management #testing: A new state assignment technique for testing and low power (SP, SC, SY, MJC), pp. 510–513.
DATE-2003-ZengZHC #correlation #performance #using: Fast Computation of Data Correlation Using BDDs (ZZ, QZ, IGH, MJC), pp. 10122–10129.
DATE-2002-CiesielskiKZR #canonical #diagrams #representation #verification: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification (MJC, PK, ZZ, BR), pp. 285–289.
DATE-2001-ZengKC #approach #named #satisfiability: LPSAT: a unified approach to RTL satisfiability (ZZ, PK, MJC), pp. 398–402.
DAC-2000-YangCS #logic #named #optimisation: BDS: a BDD-based logic optimization system (CY, MJC, VS), pp. 92–97.
DATE-2000-KallaZCH #framework #paradigm #recursion #satisfiability #using: A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm (PK, ZZ, MJC, CH), pp. 232–236.
DATE-2000-YangC #logic #synthesis: Synthesis for Mixed CMOS/PTl Logic (CY, MJC), p. 750.
DATE-1999-KallaC #equivalence #performance: Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence (PK, MJC), pp. 638–642.
DAC-1991-CiesielskiSD #approach #automaton #encoding: A Unified Approach to Input-Output Encoding for FSM State Assignment (MJC, JJS, MD), pp. 176–181.
DAC-1991-JoyC #multi: Placement for Clock Period Minimization With Multiple Wave Propagation (DAJ, MJC), pp. 640–643.
DAC-1982-CiesielskiK: An analytical method for compacting routing area in integrated circuits (MJC, EK), pp. 30–37.
DAC-1981-CiesielskiK: An optimum layer assignment for routing in ICs and PCBs (MJC, EK), pp. 733–737.