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Travelled to:
1 × Germany
Collaborated with:
C.Hsieh M.Pedram
Talks about:
microprocessor (1) analysi (1) simul (1) power (1) label (1)

Person: L. Chen

DBLP DBLP: Chen:L=

Contributed to:

DATE 20012001

Wrote 1 papers:

DATE-2001-HsiehCP #analysis #simulation
Microprocessor power analysis by labeled simulation (CTH, LC, MP), pp. 182–189.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.