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Travelled to:
1 × Germany
Collaborated with:
S.Tragoudas S.Chakravarty R.Jayabharathi
Talks about:
sequenti (1) implicit (1) circuit (1) grade (1) fault (1) exact (1) delay (1) path (1)

Person: Mahilchi Milir Vaseekar Kumar

DBLP DBLP: Kumar:Mahilchi_Milir_Vaseekar

Contributed to:

DATE 20052005

Wrote 1 papers:

DATE-2005-KumarTCJ #fault
Implicit and Exact Path Delay Fault Grading in Sequential Circuits (MMVK, ST, SC, RJ), pp. 990–995.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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